Manoj Mehrotra

SELECTIVE SILICON-GERMANIUM PROCESS AND STRUCTURE

SEMICONDUCTOR DEVICE HAVING A REDUCED HEIGHT GATE ELECTRODE LAYER

SEMICONDUCTOR DEVICE INCLUDING AN ETCH STOP LAYER FOR CONTACT HOLE FORMATION

RAISED SOURCE/DRAIN TRANSISTOR

LOW LEAKAGE SCHOTTKY DIODE

FIN TRANSISTORS WITH DOPED CONTROL LAYER FOR JUNCTION CONTROL

Fin-based laterally-diffused metal-oxide semiconductor field effect transistor

Low leakage Schottky diode

Transistor structure with silicided source and drain extensions and process for fabrication

Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance

Semiconductor structure that reduces the effects of gate cross diffusion and method of forming the structure

Semiconductor structure that reduces the effects of gate cross diffusion and method of forming the structure

Short-Resistant Metal-Gate MOS Transistor and Method of Forming the Transistor

Transistor structure with silicided source and drain extensions and process for fabrication

Multiple indium implant methods and devices and integrated circuits therefrom

Use of poly resistor implant to dope poly gates

Slim Spacer Implementation to Improve Drive Current

High threshold NMOS source-drain formation with As, P and C to reduce damage

Semiconductor doping with reduced gate edge diode leakage

Formation of nitrogen containing dielectric layers having an improved nitrogen distribution

Semiconductor device made by using a laser anneal to incorporate stress into a channel region

Multi-stage implant to improve device characteristics

Activation of CMOS source/drain extensions by ultra-high temperature anneals

P-DOPED REGION WITH IMPROVED ABRUPTNESS

Semiconductor device manufactured using a laminated stress layer

N-TYPE SEMICONDUCTOR COMPONENT WITH IMPROVED DOPANT IMPLANTATION PROFILE AND METHOD OF FORMING SAME

Method of forming a recess in a semiconductor structure

High-stress liners for semiconductor fabrication

Methods and systems for nitridation of STI liner oxide in semiconductor devices

Method for manufacturing an isolation structure using an energy beam treatment

Slim spacer implementation to improve drive current

METHOD FOR FORMING A PRE-METAL DIELECTRIC LAYER USING AN ENERGY BEAM TREATMENT

Method for manufacturing a gate sidewall spacer using an energy beam treatment

Isolation region formation that controllably induces stress in active regions

Nitridation of STI liner oxide for modulating inverse width effects in semiconductor devices

Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer

Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity

Thermal oxidation for improved silicide formation

Shallow trench isolation method

Dual salicide process for optimum performance