Chris E. BARNS

CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

REDUCTION OF LINE EDGE ROUGHNESS BY CHEMICAL MECHANICAL POLISHING

Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode

Thin III-V semiconductor films with high electron mobility

CMOS device with metal and silicide gate electrodes and a method for making it

Etch stop and hard mask film property matching to enable improved replacement metal gate process

Planarizing a semiconductor structure to form replacement metal gates

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Semiconductor substrate polishing methods and equipment

Polysilicon opening polish

Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Introducing nanotubes in trenches and structures formed thereby

Poly open polish process

Novel slurry for chemical mechanical polishing of metals

Novel slurry for chemical mechanical polishing of metals

Semiconductor substrate polishing methods and equipment

Method of forming a selectively converted inter-layer dielectric using a porogen material

Facilitating removal of sacrificial layers to form replacement metal gates

Facilitating removal of sacrificial layers via implantation to form replacement metal gates

Integrating n-type and p-type metal gate transistors

Planarizing a semiconductor structure to form replacement metal gates

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Methods for integrating replacement metal gate structures

Contact planarization for integrated circuit processing

Replacement gate process for making a semiconductor device that includes a metal gate electrode

Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a P/N junction

Selectively converted inter-layer dielectric

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Integrating n-type and p-type metal gate transistors

Replacement gate process for making a semiconductor device that includes a metal gate electrode

Selectively converted inter-layer dielectric

CMOS device with metal and silicide gate electrodes and a method for making it

Method for making a semiconductor device that includes a metal gate electrode

Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films

Methods for integrating replacement metal gate structures

Novel slurry for chemical mechanical polishing of metals

Sacrificial dielectric planarization layer

Sacrificial dielectric planarization layer

integrating n-type and P-type metal gate transistors

Integrating n-type and p-type metal gate transistors

Preventing silicide formation at the gate electrode in a replacement metal gate technology