Inventor profile of:

Lars Heineck

City:

Dresden

Country:

Germany

Published Applications:

15

Last publication date:

2008-12-25

Top Assignees for applications by Lars Heineck

The entities that hold a legal rights for patent applications filed by inventor Heineck Lars:

Recent patent applications by Heineck Lars

Lars Heineck from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2008-12-25
US20080315326A1
Electricity

Method for forming an integrated circuit having an active semiconductor device and integrated circuit

#2 | 2008-12-04
US20080299722A1
Electricity

Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure

#3 | 2008-03-13
US20080061340A1
Electricity

MEMORY CELL ARRAY AND METHOD OF FORMING THE MEMORY CELL ARRAY

#4 | 2007-12-20
US20070290249A1
Electricity

Integrated Circuit Including a Memory Cell Array

#5 | 2007-04-05
US20070077720A1
Electricity

Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure

#6 | 2007-02-08
US20070032033A1
Electricity

Connecting structure and method for manufacturing the same

#7 | 2007-02-08
US20070032032A1
Electricity

Connecting structure and method for manufacturing the same

#8 | 2006-12-21
US20060284225A1
Electricity

Memory cell array and method of forming the same

#9 | 2006-12-07
US20060276019A1
Electricity

Method for production of contacts on a wafer

#10 | 2006-08-22
US10739477
-

Method for production of contacts on a wafer

#11 | 2006-06-29
US20060141756A1
Electricity

Method for producing a semiconductor structure

#12 | 2005-07-19
US10630373
-

Semiconductor trench structure

#13 | 2005-07-12
US10722360
-

Method for fabricating a trench capacitor with an insulation collar

#14 | 2005-02-03
US20050026373A1
Electricity

Method for fabricating transistors of different conduction types and having different packing densities in a semiconductor substrate

#15 | 2005-01-06
US20050003308A1
Electricity

Method for fabricating a contact hole plane in a memory module

InventorID:

4135650 ⎘