Markus Lenski

Front-end-of-line device structure and method of forming such a front-end-of-line device structure

Methods for fabricating integrated circuits with robust gate electrode structure protection

Method of forming a semiconductor structure including silicided and non-silicided circuit elements

PROTECTION OF THE GATE STACK ENCAPSULATION

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions

Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions

Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material

Spacer for a gate electrode having tensile stress and a method of forming the same

Superior stability of characteristics of transistors having an early formed high-K metal gate

Method for making high-K metal gate electrode structures by separate removal of placeholder materials

NiSi rework procedure to remove platinum residuals

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

Methods of forming metal silicide regions on semiconductor devices

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Work function adjustment in high-K metal gate electrode structures by selectively removing a barrier layer

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas

Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material

High-K metal gate electrode structures formed by cap layer removal without sacrificial spacer

Oxide deposition by using a double liner approach for reducing pattern density dependence in sophisticated semiconductor devices

Increasing robustness of a dual stress liner approach in a semiconductor device by applying a wet chemistry

Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy deposition

Maintaining Integrity of a High-K Gate Stack After Embedding a Stressor Material by Using a Liner

Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation

Semiconductor device formed by a replacement gate approach based on an early work function metal

Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy

Cap removal in a high-k metal gate electrode structure by using a sacrificial fill material

Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

Method of manufacturing a CMOS device including molecular storage elements in a via level

Using high-k dielectrics as highly selective etch stop materials in semiconductor devices

Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning

Work function adjustment in high-k metal gate electrode structures by selectively removing a barrier layer

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device

Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material

Reducing transistor junction capacitance by recessing drain and source regions

Enhancing integrity of a high-k gate stack by confining a metal cap layer after deposition

Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Transistor with embedded Si/Ge material having reduced offset to the channel region

Method of optimizing sidewall spacer size for silicide proximity with in-situ clean

Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography steps

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

INCREASING ETCH SELECTIVITY DURING THE PATTERNING OF A CONTACT STRUCTURE OF A SEMICONDUCTOR DEVICE

Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation

Reducing transistor junction capacitance by recessing drain and source regions

Blocking pre-amorphization of a gate electrode of a transistor

Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniques

Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations

Method of patterning gate electrodes by reducing sidewall angles of a mask layer

Transistor having a channel with biaxial strain induced by silicon/germanium in the gate electrode

Method for reducing silicide defects by removing contaminants prior to drain/source activation

Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors

Technique for forming a contact insulation layer with enhanced stress transfer efficiency

Method of forming sidewall spacers

Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same

Method of forming sidewall spacers

Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique

Spacer for a gate electrode having tensile stress and a method of forming the same