Nick Lindert

Self-aligned build-up of topographic features

FORMATION OF DRAM CAPACITOR AMONG METAL INTERCONNECT

Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer

Rectangular capacitors for dynamic random access (DRAM) and dual-pass lithography methods to form the same

ATOMIC LAYER DEPOSITION (ALD) OF TAALC FOR CAPACITOR INTEGRATION

FULLY ENCAPSULATED CONDUCTIVE LINES

Formation of DRAM capacitor among metal interconnect

Metal-insulator-metal (MIM) capacitor with insulator stack having a plurality of metal oxide layers

Embedded memory device having MIM capacitor formed in excavated structure

Penetrating implant for forming a semiconductor device

SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED DOUBLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME

SEMICONDUCTOR STRUCTURE HAVING A CAPACITOR AND METAL WIRING INTEGRATED IN A SAME DIELECTRIC LAYER

Capacitor with recessed plate portion for dynamic random access memory (DRAM) and method to form the same

RECTANGULAR CAPACITORS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND DUAL-PASS LITHOGRAPHY METHODS TO FORM THE SAME

RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) IN REPLACEMENT METAL GATE (RMG) LOGIC FLOW

Penetrating implant for forming a semiconductor device

Methods to form memory devices having a capacitor with a recessed electrode

Embedded memory device having MIM capacitor formed in excavated structure

Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow

Common plate capacitor array connections, and processes of making same

Forming abrupt source drain metal gate transistors

Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby

Penetrating implant for forming a semiconductor device

MULTI-GATE TRANSISTOR WITH STRAINED BODY

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Metal gate transistors with raised source and drain regions formed on heavily doped substrate

Plasma implantated impurities in junction region recesses

Trench isolation structure having an expanded portion thereof

Fabricating strained channel epitaxial source/drain transistors

Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance

Epitaxially deposited source/drain

Plasma implantation of impurities in junction region recesses

Pre-etch implantation damage for the removal of thin film layers

Metal gate transistors with epitaxial source and drain regions

Method of forming abrupt source drain metal gate transistors

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Creating shallow junction transistors

Fabricating strained channel epitaxial source/drain transistors

Creating shallow junction transistors

Controlled faceting of source/drain regions

Epitaxially deposited source/drain