Inventor profile of:

Luca De Santis

City:

Avezzano

Country:

Italy

Published Applications:

86

Last publication date:

2026-04-23

Top Assignees for applications by Luca De Santis

The entities that hold a legal rights for patent applications filed by inventor De Santis Luca:

Recent patent applications by De Santis Luca

Luca De Santis from Avezzano, IT has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-23
US20260111151A1
Physics

PAGED STATUS INFORMATION FORMAT IN A MEMORY DEVICE

#2 | 2023-04-06
US20230105956A1
Physics

Apparatuses and methods for concurrently accessing different memory planes of a memory

#3 | 2022-12-22
US20220405013A1
Physics

Asynchronous interrupt event handling in multi-plane memory devices

#4 | 2022-04-21
US20220122665A1
Physics

Memory devices for pattern matching based on majority of cell pair match

#5 | 2022-03-31
US20220100760A1
Physics

Acceleration of data queries in memory

#6 | 2022-03-17
US20220083241A1
Physics

Power budget arbitration for multiple concurrent access operations in a memory device

#7 | 2022-01-13
US20220011970A1
Physics

Checking status of multiple memory dies in a memory sub-system

#8 | 2021-12-09
US20210383876A1
Physics

Apparatus for determining data states of memory cells

#9 | 2021-10-07
US20210312994A1
Physics

Apparatus for determining an expected data age of memory cells

#10 | 2021-07-15
US20210217475A1
Physics

Memory devices for pattern matching

#11 | 2021-07-08
US20210210143A1
Physics

Memories configured to perform concurrent access operations on different groupings of memory cells

#12 | 2021-06-17
US20210183452A1
Physics

Memory devices for comparing input data to data stored in memory cells coupled to a data line

#13 | 2021-04-08
US20210103389A1
Physics

Partially written block treatment

#14 | 2021-03-25
US20210090656A1
Physics

Memory cells configured to generate weighted inputs for neural networks

#15 | 2021-03-25
US20210090623A1
Physics

Apparatuses and methods for concurrently accessing different memory planes of a memory

#16 | 2020-12-31
US20200411098A1
Physics

Apparatus and methods for performing concurrent access operations on different groupings of memory cells

#17 | 2020-11-26
US20200372960A1
Physics

Memory configured to perform logic operations on values representative of sensed characteristics of data lines and a threshold data value

#18 | 2020-10-22
US20200335171A1
Physics

Apparatus for determining data states of memory cells

#19 | 2020-07-23
US20200234777A1
Physics

Apparatus for determining an expected data age of memory cells

#20 | 2020-07-02
US20200211648A1
Physics

Memory cells configured to generate weighted inputs for neural networks

#21 | 2020-05-14
US20200152278A1
Physics

Apparatus and methods for determining read voltages for a read operation

#22 | 2020-04-16
US20200118635A1
Physics

Methods for determining an expected data age of memory cells

#23 | 2020-02-04
US16161256
Physics

Apparatus and methods for determining an expected data age of memory cells

#24 | 2019-11-14
US20190348117A1
Physics

Methods and apparatus for pattern matching in a memory containing sets of memory elements

#25 | 2019-11-07
US20190341115A1
Physics

Memory configured to generate a data value from a data line connected to more than one string of series-connected memory cells

#26 | 2019-10-24
US20190325971A1
Physics

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

#27 | 2019-09-19
US20190286328A1
Physics

Partially written block treatment

#28 | 2019-09-05
US20190272877A1
Physics

Memory as a programmable logic device

#29 | 2019-08-29
US20190267102A1
Physics

Determining data states of memory cells

#30 | 2019-03-07
US20190074069A1
Physics

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

#31 | 2019-03-07
US20190074068A1
Physics

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

#32 | 2019-02-28
US20190066804A1
Physics

Determining data states of memory cells

#33 | 2019-02-14
US20190050162A1
Physics

Configurable operating mode memory device and methods of operation

#34 | 2019-02-07
US20190042156A1
Physics

Power down/power-loss memory controller

#35 | 2019-01-17
US20190018733A1
Physics

High performance memory controller

#36 | 2019-01-03
US20190004938A1
Physics

Read and program operations in a memory device

#37 | 2018-12-20
US20180366167A1
Physics

Apparatuses and methods for concurrently accessing different memory planes of a memory

#38 | 2018-12-20
US20180365293A1
Physics

Memory devices for pattern matching

#39 | 2018-11-08
US20180322922A1
Physics

Methods and apparatus for pattern matching having memory cell pairs coupled in series and coupled in parallel

#40 | 2018-10-11
US20180294035A1
Physics

Methods of operating memory

#41 | 2018-10-11
US20180294032A1
Physics

Memory as a programmable logic device

#42 | 2018-08-28
US15692154
Physics

Determining data states of memory cells

#43 | 2018-08-09
US20180225056A1
Physics

Configurable operating mode memory device and methods of operation

#44 | 2018-07-26
US20180210653A1
Physics

Partially written block treatment

#45 | 2018-05-08
US13774688
Physics

Memory device having a controller to enable and disable mode control circuitry of the controller

#46 | 2018-04-19
US20180108415A1
Physics

Methods and apparatus for pattern matching using redundant memory elements

#47 | 2018-01-23
US14991007
Physics

Methods for pattern matching using multiple cell pairs

#48 | 2017-12-21
US20170365342A1
Physics

Memory as a programmable logic device

#49 | 2017-12-21
US20170364268A1
Physics

Memory devices having distributed controller systems

#50 | 2017-10-26
US20170309341A1
Physics

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

#51 | 2017-09-21
US20170270983A1
Physics

Apparatuses and methods for concurrently accessing different memory planes of a memory

#52 | 2017-08-17
US20170235637A1
Physics

High performance memory controller

#53 | 2016-12-22
US20160371335A1
Physics

Memory devices for pattern matching

#54 | 2016-12-08
US20160358661A1
Physics

Methods of operating memory

#55 | 2016-09-15
US20160267993A1
Physics

Apparatus and methods of operating memory for exact and inexact searching of feature vectors

#56 | 2016-09-15
US20160267953A1
Physics

Single node power management for multiple memory devices

#57 | 2016-09-15
US20160266966A1
Physics

High performance memory controller

#58 | 2016-09-06
US13449082
Physics

Methods and apparatus for pattern matching

#59 | 2016-08-30
US13774553
Physics

Neural network in a memory device

#60 | 2016-08-11
US20160232978A1
Physics

Memory as a programmable logic device

#61 | 2016-08-11
US20160231930A1
Physics

Methods for operating a distributed controller system in a memory device

#62 | 2016-08-02
US13864605
Physics

Using do not care data with feature vectors

#63 | 2016-05-31
US13864444
Physics

Searching using multilevel cells and programming multilevel cells for searching

#64 | 2016-05-17
US13774636
Physics

Memory as a programmable logic device

#65 | 2016-03-03
US20160064052A1
Physics

Single node power management for multiple memory devices

#66 | 2016-02-18
US20160048343A1
Physics

Apparatuses and methods for concurrently accessing different memory planes of a memory

#67 | 2015-11-19
US20150331792A1
Physics

Memory devices with register banks storing actuators that cause operations to be performed on a memory core

#68 | 2015-11-05
US20150318047A1
Physics

Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods

#69 | 2015-08-11
US13864659
Physics

Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods

#70 | 2014-06-05
US20140156904A1
Physics

Bus controller

#71 | 2014-05-15
US20140133226A1
Physics

Erasing physical memory blocks of non-volatile memory

#72 | 2014-01-30
US20140032886A1
Physics

Memory controllers

#73 | 2013-08-29
US20130227203A1
Physics

Dynamic SLC/MLC blocks allocations for non-volatile memory

#74 | 2012-05-24
US20120131267A1
Physics

Memory device distributed controller system

#75 | 2012-02-02
US20120026792A1
Physics

Erase cycle counter usage in a memory device

#76 | 2010-09-30
US20100246265A1
Physics

Erase cycle counter usage in a memory device

#77 | 2010-07-08
US20100174855A1
Physics

Memory device controller

#78 | 2010-06-03
US20100138623A1
Physics

Memory area protection system and methods

#79 | 2010-05-13
US20100122016A1
Physics

Dynamic SLC/MLC blocks allocations for non-volatile memory

#80 | 2008-12-04
US20080298130A1
Physics

Memory device distributed controller system

#81 | 2007-09-13
US20070211529A1
Physics

Memory device distributed controller system

#82 | 2007-02-15
US20070038828A1
Physics

Chip protection register lock circuit in a flash memory device

#83 | 2006-11-16
US20060259714A1
Physics

Memory device controller

#84 | 2005-10-27
US20050240851A1
Physics

ROM-based controller monitor in a memory device

#85 | 2005-06-23
US20050138274A1
Physics

Chip protection register lock circuit in a flash memory device

#86 | 2005-01-20
US20050015541A1
Physics

Memory device controller

InventorID:

419310 ⎘