Dale E. Gulick

Initialization of a computer system including a secure execution mode-capable processor

Computer system including a secure execution mode-capable CPU and a security services processor connected via a secure communication path

Embedded Processor with Direct Connection of Security Devices for Enhanced Security

System including a host connected to a plurality of memory modules via a serial memory interconnect

Processing tasks with failure recovery

Computer system including a bus bridge for connection to a security services processor

Configuring a communication link interface

Processing tasks with failure recovery

Flexible probe/probe response routing for maintaining coherency

Remote management mechanism to prevent illegal system commands

Enhanced security and manageability using secure storage in a personal computer system

Controlling the replacement of prefetched descriptors in a cache

ASF state determination using chipset-resident watchdog timer

Message based power management in a multi-processor system

Method and apparatus for configuring a peripheral bus

External locking mechanism for personal computer memory locations

Use of a signal line to adjust width and/or frequency of a communication link during system operation

Serial bus host controller diagnosis

Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions

Microcomputer bridge for remote manageability

Secure execution box

Message based power management

Resource sequester mechanism

Secure booting of a personal computer system

Managing a controller embedded in a bridge

Locking mechanism override and disable for personal computer ROM access protection

Method and apparatus for impedance matching in systems configured for multiple processors

Transaction duration management in a USB host controller

Cryptographic randomness register for computer system security

Microcomputer bridge architecture with an embedded microcontroller

Method and apparatus for extending legacy computer systems

Reciprocally adjustable dual queue mechanism

Hardware interlock mechanism using a watchdog timer

Direct transaction mode for peripheral devices

Computer system employing a trusted execution environment including a memory controller configured to clear memory

Interruptable and re-enterable system management mode programming code

I/O node for a computer system including an integrated graphics engine and an integrated I/O hub