Williston, Vermont
United States
21
2024-10-15
The entities that hold a legal rights for patent applications filed by inventor Wohl Peter:
Peter Wohl from Williston, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST)
#2 | 2024-04-04Distributed test pattern generation and synchronization
#3 | 2022-10-20Multi-cycle test generation and source-based simulation
#4 | 2018-06-07Increasing compression by reducing padding patterns
#5 | 2016-01-28Diagnosis and debug with truncated simulation
#6 | 2015-03-05Diagnosis and debug using truncated simulation
#7 | 2014-09-18Two-level compression through selective reseeding
#8 | 2013-10-10Fully X-tolerant, very high scan compression scan test systems and techniques
#9 | 2013-09-05ATPG and compression by using majority gates
#10 | 2013-09-05Increasing PRPG-based compression by delayed justification
#11 | 2011-10-20Fully X-tolerant, very high scan compression scan test systems and techniques
#12 | 2011-09-22Increasing PRPG-based compression by delayed justification
#13 | 2010-04-22Fully X-tolerant, very high scan compression scan test systems and techniques
#14 | 2010-04-01Increasing scan compression by using X-chains
#15 | 2008-12-25Launch-on-shift support for on-chip-clocking
#16 | 2008-10-16Scan compression circuit and method of design therefor
#17 | 2008-10-16Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit
#18 | 2007-06-26Deterministic BIST architecture tolerant of uncertain scan chain outputs
#19 | 2006-01-31Deterministic bist architecture including MISR filter
#20 | 2005-10-25Method and system for generating an ATPG model of a memory from behavioral descriptions
#21 | 2005-09-27Efficient compression and application of deterministic patterns in a logic BIST architecture
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