La Crescenta, California
United States
38
2026-04-30
The entities that hold a legal rights for patent applications filed by inventor Beach Robert:
Robert Beach from La Crescenta, US has applied for patents for these inventions. The list has both pending applications and granted patents:
GaN HEMT WITH REDUCED THRESHOLD SHIFTING
#2 | 2025-12-04GaN HEMT WITH LOW THRESHOLD VOLTAGE SHIFT USING A HOLE INJECTOR/COLLECTOR
#3 | 2025-08-28GaN DEVICE WITH HOLE ELIMINATION CENTERS
#4 | 2024-12-12GaN TRANSISTOR HAVING MULTI-THICKNESS FRONT BARRIER
#5 | 2024-08-15GaN DEVICE WITH HOLE ELIMINATION CENTERS
#6 | 2023-04-13BIDIRECTIONAL GaN FET WITH SINGLE GATE
#7 | 2020-03-05Cascaded bootstrapping GaN power switch and driver
#8 | 2019-08-15Semiconductor devices with back surface isolation
#9 | 2018-12-20Enhancement-mode GaN transistor with selective and nonselective etch layers for improved uniformity in GaN spacer thickness
#10 | 2017-12-07Multi-step surface passivation structures and methods for fabricating same
#11 | 2017-11-16GaN transistors with polysilicon layers used for creating additional components
#12 | 2017-06-08Semiconductor devices with back surface isolation
#13 | 2016-04-21Integrated circuit with matching threshold voltages and method for making same
#14 | 2016-03-24GaN transistors with polysilicon layers used for creating additional components
#15 | 2016-01-28Fabrication of semiconductor device using alternating high and low temperature layers
#16 | 2015-12-10Fabrication of III-Nitride Power Semiconductor Device
#17 | 2015-09-24Flip chip interconnection with reduced current density
#18 | 2015-06-18High performance III-nitride power device
#19 | 2015-05-14III-Nitride Semiconductor Device Fabrication
#20 | 2015-02-05Fabrication of III-nitride semiconductor device and related structures
#21 | 2015-02-05Integrated circuit with matching threshold voltages and method for making same
#22 | 2015-01-29GaN device with reduced output capacitance and process for making same
#23 | 2015-01-29GaN transistors with polysilicon layers for creating additional components
#24 | 2015-01-08Method to fabricate self-aligned isolation in gallium nitride devices and integrated circuits
#25 | 2015-01-08Isolation structure in gallium nitride devices and integrated circuits
#26 | 2014-09-18III-Nitride Heterojunction Device
#27 | 2014-04-17Fabrication of III-nitride semiconductor device and related structures
#28 | 2013-09-12Enhancement mode GaN HEMT device
#29 | 2012-08-02Ion implanted and self aligned gate structure for GaN transistors
#30 | 2012-07-12Enhancement mode GaN HEMT device with gate spacer and method for fabricating the same
#31 | 2012-06-21Semiconductor devices with back surface isolation
#32 | 2011-10-13VIA STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#33 | 2010-10-14Dopant diffusion modulation in GaN buffer layers
#34 | 2010-10-14Compensated gate MISFET and method for fabricating the same
#35 | 2010-10-14Bumped, self-isolated GaN transistor chip with electrically isolated back surface
#36 | 2010-10-14Enhancement mode GaN HEMT device and method for fabricating the same
#37 | 2010-10-14Enhancement mode gallium nitride transistor with improved gate characteristics
#38 | 2010-10-14Back diffusion suppression structures
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