Babette van Antwerpen

Enhanced Adaptive Logic Circuitry with Improved Function Coverage and Packing Ability

FPGA Compiler Flow for Heterogeneous Programmable Logic Elements

Systems And Methods For Tracking Synthesis Optimizations For Circuit Designs

Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement

Register retiming technique

Method and apparatus for performing parallel synthesis on a field programmable gate array

Register retiming technique

Methods and apparatus for error checking code decomposition

Tracing and reporting registers removed during synthesis

Local searching techniques for technology mapping

Register retiming technique

Recognizing muliplexers

Register retiming technique

Methods and apparatus for error checking code decomposition

Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage

User-directed timing-driven synthesis

State machine recognition and optimization

Local searching techniques for technology mapping

Method and apparatus for reducing synthesis runtime

Physical resynthesis of a logic design

Timing-driven synthesis with area trade-off

Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage

Fast method for functional mapping to incomplete LUT pairs

Estimating quality during early synthesis

Register retiming technique