Uwe Griebenow

Semiconductor device comprising a stacked die configuration including an integrated peltier element

Field effect transistors for a flash memory comprising a self-aligned charge storage region

High-K gate electrode structure formed after transistor fabrication by using a spacer

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

Method for increasing penetration depth of drain and source implantation species for a given gate height

Asymmetric transistor devices formed by asymmetric spacers and tilted implantation

Method and Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner Approach

Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

Field effect transistors for a flash memory comprising a self-aligned charge storage region

Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials

Method for forming a transistor with recessed drain and source areas and non-conformal metal silicide regions

Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition

Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal

High-K metal gate electrode structures formed at different process stages of a semiconductor device

Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors

Enhanced confinement of sensitive materials of a high-K metal gate electrode structure

REDUCING THE SERIES RESISTANCE IN SOPHISTICATED TRANSISTORS BY EMBEDDING METAL SILICIDE CONTACT REGIONS RELIABLY INTO HIGHLY DOPED SEMICONDUCTOR MATERIAL

Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers

TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SUPERIOR IMPLANTATION MASKING EFFECT

Semiconductor device comprising a buried waveguide for device internal optical communication

Optical signal transfer in a semiconductor device by using monolithic opto-electronic components

Stress adjustment in stressed dielectric materials of semiconductor devices by stress relaxation based on radiation

Reduced silicon thickness of N-channel transistors in SOI CMOS devices

In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profile

Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch

Method for adjusting the height of a gate electrode in a semiconductor device

High-K gate electrode structure formed after transistor fabrication by using a spacer

Recessed drain and source areas in combination with advanced silicide formation in transistors

Stress transfer enhancement in transistors by a late gate re-crystallization

Asymmetric transistor devices formed by asymmetric spacers and tilted implantation

CMOS DEVICE COMPRISING NMOS TRANSISTORS AND PMOS TRANSISTORS HAVING INCREASED STRAIN-INDUCING SOURCES AND CLOSELY SPACED METAL SILICIDE REGIONS

Transistor having a high-k metal gate stack and a compressively stressed channel

Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active region

TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES IN POLYSILICON GATE ELECTRODES BY AN INTERMEDIATE DIFFUSION BLOCKING LAYER

Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND NON-CONFORMAL METAL SILICIDE REGIONS

Drive current increase in transistors by asymmetric amorphization implantation

DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE REGION BY LOCALLY INDUCING DIFFERENT LATERAL STRAIN LEVELS IN THE ACTIVE REGION

REDUCTION OF METAL SILICIDE DIFFUSION IN A SEMICONDUCTOR DEVICE BY PROTECTING SIDEWALLS OF AN ACTIVE REGION

Method of detecting repeating defects in lithography masks on the basis of test substrates exposed under varying conditions

Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device

Method for increasing penetration depth of drain and source implantation species for a given gate height

CMOS DEVICE COMPRISING AN NMOS TRANSISTOR WITH RECESSED DRAIN AND SOURCE AREAS AND A PMOS TRANSISTOR HAVING A SILICON/GERMANIUM MATERIAL IN THE DRAIN AND SOURCE AREAS

Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region

Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach

METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE

Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region

Technique for enhancing transistor performance by transistor specific contact design