Inventor profile of:

Andre Schaefer

City:

Braunschweig

Country:

Germany

Published Applications:

22

Last publication date:

2017-01-12

Top Assignees for applications by Andre Schaefer

The entities that hold a legal rights for patent applications filed by inventor Schaefer Andre:

Recent patent applications by Schaefer Andre

Andre Schaefer from Braunschweig, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2017-01-12
US20170011779A1
Physics

Power management in multi-die assemblies

#2 | 2015-12-10
US20150357011A1
Physics

Techniques for accessing a dynamic random access memory array

#3 | 2015-11-05
US20150317228A1
Physics

Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems

#4 | 2015-06-18
US20150170729A1
Physics

Techniques for accessing a dynamic random access memory array

#5 | 2015-05-14
US20150130534A1
Electricity

Interlayer communications for 3D integrated circuit stack

#6 | 2015-04-23
US20150108660A1
Electricity

Stacked memory with interface providing offset interconnects

#7 | 2015-01-01
US20150003181A1
Physics

Power management in multi-die assemblies

#8 | 2014-10-30
US20140325136A1
Physics

Configuration for power reduction in DRAM

#9 | 2014-09-18
US20140281193A1
Physics

System and method for accessing memory

#10 | 2014-07-03
US20140185392A1
Physics

Memory sense amplifier voltage modulation

#11 | 2014-07-03
US20140183691A1
Electricity

Resonant clocking for three-dimensional stacked devices

#12 | 2014-04-03
US20140092574A1
Physics

Integrated voltage regulators with magnetically enhanced inductors

#13 | 2014-01-02
US20140006702A1
Physics

Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems

#14 | 2014-01-02
US20140006700A1
Physics

Configuration for power reduction in DRAM

#15 | 2013-12-19
US20130335059A1
Physics

Fully integrated voltage regulators for multi-stack integrated circuit architectures

#16 | 2013-11-07
US20130293292A1
Electricity

Interlayer communications for 3D integrated circuit stack

#17 | 2013-10-24
US20130279276A1
Physics

Separate microchannel voltage domains in stacked memory architecture

#18 | 2013-10-17
US20130272049A1
Physics

Stacked memory with interface providing offset interconnects

#19 | 2013-09-19
US20130246734A1
Physics

Adaptive address mapping with dynamic runtime memory mapping selection

#20 | 2012-10-04
US20120250443A1
Physics

Energy efficient power distribution for 3D integrated circuit stack

#21 | 2011-06-23
US20110153908A1
Physics

Adaptive address mapping with dynamic runtime memory mapping selection

#22 | 2010-12-30
US20100332921A1
Physics

Fast data eye retraining for a memory

InventorID:

448509 ⎘