Jeffrey W. Scott

Configurable pipeline based on error detection mode in a data processing system

Data processing system having dynamic thread control

Data processing system with speculative fetching

Systems and methods for managing return stacks in a multi-threaded data processing system

Systems and methods for processing both instructions and constant values from a memory of a digital processor accessed by separate pointers

METHOD OF OPERATING A MULTI-THREAD CAPABLE PROCESSOR SYSTEM, AN AUTOMOTIVE SYSTEM COMPRISING SUCH MULTI-THREAD CAPABLE PROCESSOR SYSTEM, AND A COMPUTER PROGRAM PRODUCT

Selectively performing a single cycle write operation with ECC in a data processing system

Integrated circuit processor and method of operating the integrated circuit processor in different modes of differing thread counts

System and method for selectively allocating entries at a branch target buffer

SYSTEMS AND METHODS FOR MANAGING BRANCH TARGET BUFFERS IN A MULTI-THREADED DATA PROCESSING SYSTEM

Data processor device having a debug control module which selectively modifies trace messages

Systems and methods for locking branch target buffer entries

Partitioned radio-frequency apparatus and associated methods

Data processor device for handling a watchpoint and method thereof

Data processor device for handling a watchpoint and method thereof

Random timeslot controller for enabling built-in self test module

Random access of a cache portion using an access module

Processor executing instructions in ALU in first/second pipeline stage during non-ECC/ECC mode

Radio-frequency apparatus and associated methods

Using built-in self test for preventing side channel security attacks on multi-processor systems

Executing misaligned load dependent instruction in second execution stage in parity protected mode in configurable pipelined processor

Partitioned radio-frequency apparatus and associated methods

Result forwarding to dependent instruction in pipelined processor with mode selectable execution in E1 or E2 of pipelined operational stages

Digital architecture for radio-frequency apparatus and associated methods

Branch target buffer allocation

Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access

SELECTIVELY PERFORMING A SINGLE CYCLE WRITE OPERATION WITH ECC IN A DATA PROCESSING SYSTEM

Selective postponement of branch target buffer (BTB) allocation

Metric for selective branch target buffer (BTB) allocation

Method and apparatus for handling shared hardware and software debug resource events in a data processing system

Branch target buffer addressing in a data processor

SELECTIVE GUARDED MEMORY ACCESS ON A PER-INSTRUCTION BASIS

Partitioned radio-frequency apparatus and associated methods

Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with switchable DC termination impedance

Direct digital access arrangement circuitry and method for connecting to phone lines

Selective cache line allocation instruction execution and circuitry

Direct digital access arrangement circuitry and method for connecting to phone lines

Data processor having dynamic control of instruction prefetch buffer depth and method therefor

Partitioning of radio-frequency apparatus

DC offset reduction in radio-frequency apparatus and associated methods

Isolation system with digital communication across a capacitive barrier

Direct digital access arrangement circuitry and method for connecting to phone lines

Partitioning of radio-frequency apparatus

Calibrated low-noise current and voltage references and associated methods

Digital interface in radio-frequency apparatus and associated methods

Isolation system with digital communication across a capacitive barrier

Apparatus and methods for output buffer circuitry with constant output power in radio-frequency circuitry

Processing system having sequential address indicator signals

Direct digital access arrangement circuitry and method for connecting to phone lines

Apparatus and methods for generating radio frequencies in communication circuitry using multiple control signals

Direct digital access arrangement circuitry and method for connecting to phone lines

Digital architecture for radio-frequency apparatus and associated methods

Digital isolation system with hybrid circuit in ADC calibration loop

Digital access arrangement circuitry and method having current ramping control of the hookswitch

Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with switchable time constants

Method and apparatus for interfacing a processor to a coprocessor

Apparatus and method for front-end circuitry in radio-frequency apparatus

Apparatus and methods for calibrating signal-processing circuitry

Notch filter for DC offset reduction in radio-frequency apparatus and associated methods

Method and apparatus for interfacing a processor to a coprocessor

Digital isolation system with ADC offset calibration

Apparatus for generating multiple radio frequencies in communication circuitry and associated methods

Direct digital access arrangement circuitry and method for connecting DSL circuitry to phone lines

Architecture for minimum loop current during ringing and caller ID

Digital architecture for radio-frequency apparatus and associated methods

Loop current monitor circuitry and method for a communication system

Separation of ring detection functions across isolation barrier for minimum power

Method and apparatus for allocating entries in a branch target buffer

Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with programmable current limiting

Data processing system having redirecting circuitry and method therefor

Processor having selective branch prediction

Direct digital access arrangement circuitry and method for connecting DSL circuitry to phone lines

Partitioned radio-frequency apparatus and associated methods