RAMBUS INC.

SYSTEM APPLICATION OF DRAM COMPONENT WITH CACHE MODE

Stacked semiconductor device assembly in computer system

Structure for delivering power

Method and apparatus for camouflaging an integrated circuit using virtual camouflage cells

Physically unclonable camouflage structure and methods for fabricating same

Memory system topologies including a buffer device and an integrated circuit memory device

Unsuccessful write retry buffer

Image sensor having sub-diffraction-limit pixels

Multi-bit symbol reception using remotely-sourced reference signals

Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid

Asymmetrically masked multiplication

Skew-tolerant timing signal gating

Pseudo-differential signaling for modified single-ended interface

Buffer circuit with data bit inversion

Fractional-readout oversampled image sensor

Symbol-rate phase detector for multi-PAM receiver

Domain-distributed cryogenic signaling amplifier

On-die termination

Reduced current memory device

Method and apparatus for calibrating write timing in a memory system

Variable width memory module supporting enhanced error detection and correction

Memory controller for strobe-based memory systems

Periodic calibration for communication channels by drift tracking

Transaction-based on-die termination

Selectable-tap equalizer

Memory controller

Memory module threading with staggered data transfers

Communication channel calibration for drift conditions

Calibration methods and circuits to calibrate drive current and termination impedance

Memory controller systems with nonvolatile memory for storing operating parameters

Stacked DRAM device and method of manufacture

Maintenance operations in a DRAM

Hybrid memory module with improved inter-memory data transmission path

Local internal discovery and configuration of individually selected and jointly selected devices

Integrated circuit with configurable on-die termination

Adaptive equalization using correlation of data patterns with errors

Methods and circuits for adaptive equalization

Interface for bridging out-of-band information from a downstream communication link to an upstream communication link

Memory module with reduced read/write turnaround overhead

High capacity memory system with improved command-address and chip-select signaling mode

Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid

Testing through-silicon-vias

Memory system topologies including a buffer device and an integrated circuit memory device

Dual-domain memory

Wide range frequency synthesizer with quadrature generation and spur cancellation

Memory system design using buffer(S) on a mother board

Frequency-agile clock generator

Dual temperature band integrated circuit device

Variable resolution digital equalization

Buffering device with status communication method for memory controller

Phase adjustment for interleaved analog to digital converters

Method and apparatus for source-synchronous signaling

Reduced transport energy in a memory system

Equalizing transmitter and method of operation

Frequency-agile clock multiplier

Multi-die memory device

Module based data transfer

Bidirectional signaling with asymmetric termination

Memory device comprising programmable command-and-address and/or data interfaces

Methods and apparatus for synchronizing communication with a memory controller

Clock generation for timing communications with ranks of memory devices

Systems and methods for lensed and lensless optical sensing of binary scenes

Load reduced memory module

Amplifier circuit for cryogenic applications

Signal receiver with skew-tolerant strobe gating

Low power logic circuitry

Protocol for memory power-mode control

Memory component with multiple command/address sampling modes

Methods and circuits for asymmetric distribution of channel equalization between devices

High-speed signaling systems and methods with adaptable, continuous-time equalization

Phase calibration of clock signals

Low-noise, high dynamic-range image sensor

Flash controller to provide a value that represents a parameter to a flash memory

Serial link receiver with improved bandwidth and accurate eye monitor

Receiver with time-varying threshold voltage

Baseline wander correction

Protocol for memory power-mode control

Forwarding signal supply voltage in data transmission system

On-die termination of address and command signals

Memory systems and methods for improved power management

Shared-counter image sensor

Selectabe-tap equalizer

Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling

Cache memory that supports tagless addressing

Memory controller with error detection and retry modes of operation

Hybrid memory module with improved inter-memory data transmission path

Memory controller with staggered request signal output

Using dynamic bursts to support frequency-agile memory interfaces

Stacked semiconductor device assembly in computer system

Configurable pipeline based on error detection mode in a data processing system

Direct sequence detection and equalization

Memory component with on-die termination

Dark-emulation image sensor

Protocol for refresh between a memory controller and a memory

Memory component with independently enabled data and command interfaces

System and method for providing a configurable timing control for a memory system

High-throughput low-latency hybrid memory module

Buffering device with status communication method for memory controller

Maintenance operations in a DRAM

Controller to detect malfunctioning address of memory device