Inventor profile of:

Steven E. Molnar

City:

Chapel Hill, North Carolina

Country:

United States

Published Applications:

79

Last publication date:

2025-11-20

Top Assignees for applications by Steven E. Molnar

The entities that hold a legal rights for patent applications filed by inventor Molnar Steven E.:

Recent patent applications by Molnar Steven E.

Steven E. Molnar from Chapel Hill, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-11-20
US20250358228A1
Electricity

DYNAMIC MEMORY BANDWIDTH SHAPING

#2 | 2025-05-15
US20250156326A1
Physics

MANAGING A SYSTEM LEVEL CACHE

#3 | 2025-05-15
US20250156321A1
Physics

MANAGING A PROGRAMMABLE CACHE CONTROL MAPPING TABLE IN A SYSTEM LEVEL CACHE

#4 | 2023-10-05
US20230315328A1
Physics

HIGH BANDWIDTH EXTENDED MEMORY IN A PARALLEL PROCESSING SYSTEM

#5 | 2017-04-06
US20170097896A1
Physics

Storing secure state information in translation lookaside buffer cache lines

#6 | 2015-07-16
US20150199280A1
Physics

Method and system for implementing multi-stage translation of virtual addresses

#7 | 2015-06-16
US11555639
Physics

Coalescing to avoid read-modify-write during compressed data operations

#8 | 2015-01-06
US12649204
-

Coalescing to avoid read-modify-write during compressed data operations

#9 | 2014-10-14
US12340503
-

Compression status caching

#10 | 2014-09-18
US20140281319A1
Physics

System and method for protecting data by returning a protect signal with the data

#11 | 2014-07-03
US20140184601A1
Physics

System and method for frame buffer decompression and/or compression

#12 | 2014-06-24
US12773712
-

Hardware-managed virtual buffers using a shared memory for load distribution

#13 | 2014-06-05
US20140152652A1
Physics

Order-preserving distributed rasterizer

#14 | 2014-04-22
US12581700
-

Distributing primitives to multiple rasterizers

#15 | 2013-12-10
US12651367
-

Rasterization tile coalescer and reorder buffer

#16 | 2013-12-10
US12651357
-

Threshold-based lossy reduction color compression

#17 | 2013-09-26
US20130249897A1
Physics

Alternate reduction ratios and threshold mechanisms for framebuffer compression

#18 | 2013-08-13
US11593368
-

Small primitive detection to optimize compression and decompression in a graphics processor

#19 | 2013-04-23
US11954722
-

Coalescing to avoid read-modify-write during compressed data operations

#20 | 2012-12-11
US12340496
-

Zero-bandwidth clears

#21 | 2012-11-27
US12340493
-

Index-based zero-bandwidth clears

#22 | 2012-11-08
US20120284568A1
Physics

Hardware override of application programming interface programmed state

#23 | 2012-08-14
US11934051
-

Late Z testing for multiple render targets

#24 | 2012-07-31
US11934042
-

Z-test result reconciliation with multiple partitions

#25 | 2012-07-31
US11557068
-

Color-compression using automatic reduction of multi-sampled pixels

#26 | 2012-07-24
US11934046
-

Early Z testing for multiple render targets

#27 | 2012-07-24
US11625136
-

Hardware override of application programming interface programmed state

#28 | 2012-06-26
US11959441
-

Graphics rendering pipeline that supports early-Z and late-Z virtual machines

#29 | 2012-06-14
US20120147027A1
Physics

Method and system for improving data coherency in a parallel rendering system

#30 | 2012-03-20
US11556660
-

Method and system for improving data coherency in a parallel rendering system

#31 | 2012-02-02
US20120026171A1
Physics

Parallel array architecture for a graphics processor

#32 | 2011-12-27
US11556657
-

Method and system for improving data coherency in a parallel rendering system

#33 | 2011-11-15
US12175706
-

System and method for packing data in different formats in a tiled graphics memory

#34 | 2011-11-15
US11407464
-

Apparatus and method for performing blit operations across parallel processors

#35 | 2011-10-06
US20110243469A1
Physics

Selecting and representing multiple compression methods

#36 | 2011-08-16
US11953812
-

Methods and systems for reusing memory addresses in a graphics system

#37 | 2011-05-17
US11552093
-

Methods and systems for reusing memory addresses in a graphics system

#38 | 2011-04-21
US20110090251A1
Physics

Alpha-to-coverage value determination using virtual samples

#39 | 2011-04-21
US20110090250A1
Physics

Alpha-to-coverage using virtual samples

#40 | 2011-04-21
US20110090220A1
Physics

Order-preserving distributed rasterizer

#41 | 2011-04-14
US20110087840A1
Physics

Efficient line and page organization for compression status bit caching

#42 | 2011-03-29
US12614236
-

Latency tolerant pipeline synchronization

#43 | 2011-03-24
US20110072235A1
Physics

Efficient memory translator with variable size cache line coverage

#44 | 2011-02-01
US11610127
-

Blend optimizations that are conformant to floating-point rules

#45 | 2011-01-11
US11557085
-

Method and system for reducing memory bandwidth requirements in an anti-aliasing operation

#46 | 2010-11-09
US11612415
-

Connecting multiple pixel shaders to a frame buffer without a crossbar

#47 | 2010-09-28
US11467665
-

Variable performance rasterization with constant effort

#48 | 2010-04-06
US11557076
-

Color-compression using automatic reduction of multi-sampled pixels

#49 | 2010-03-23
US11493484
-

Methods of processing graphics data including reading and writing buffers

#50 | 2010-02-09
US11538002
-

Method and apparatus to ensure consistency of depth values computed in different sections of a graphics processor

#51 | 2010-01-07
US20100002000A1
Physics

Hybrid multisample/supersample antialiasing

#52 | 2010-01-07
US20100001999A1
Physics

Hybrid multisample/supersample antialiasing

#53 | 2009-12-08
US12332366
-

Optimized alpha blend for anti-aliased render

#54 | 2009-12-01
US11454225
-

Prescient cache management

#55 | 2009-11-17
US11554511
-

Latency tolerant pipeline synchronization

#56 | 2009-11-10
US11454230
-

Prescient cache management

#57 | 2009-10-01
US20090244074A1
Physics

Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation

#58 | 2009-08-11
US11955746
-

System and method for virtual coverage anti-aliasing

#59 | 2009-06-09
US11393621
-

Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation

#60 | 2009-04-14
US11556020
-

Hierarchical multi-precision pipeline counters

#61 | 2009-03-31
US11182676
-

Antialiasing using hybrid supersampling-multisampling

#62 | 2009-03-24
US10985690
-

Rendering of disjoint and overlapping blits

#63 | 2009-03-24
US10646076
-

Transparent antialiased memory access

#64 | 2009-01-20
US11105198
-

Optimized alpha blend for anti-aliased render

#65 | 2008-09-02
US11304268
-

System and method for packing data in different formats in a tiled graphics memory

#66 | 2008-07-15
US11051130
-

Apparatus, system, and method for a partitioned memory

#67 | 2008-06-03
US10878460
-

Planar z representation for z compression

#68 | 2008-05-06
US11051068
-

Apparatus, system, and method for a partitioned memory for a graphics system

#69 | 2008-02-19
US10980078
-

System and method for virtual coverage anti-aliasing

#70 | 2007-11-08
US20070257905A1
Physics

Optimizing a graphics rendering pipeline using early Z-mode

#71 | 2007-10-23
US10740229
-

System and method for packing data in a tiled graphics memory

#72 | 2007-07-12
US20070159488A1
Physics

Parallel Array Architecture for a Graphics Processor

#73 | 2006-05-30
US10737418
-

Position conflict detection and avoidance in a programmable graphics processor using tile coverage data

#74 | 2006-05-30
US10736006
-

Position conflict detection and avoidance in a programmable graphics processor

#75 | 2006-01-31
US10198707
-

Integrated graphics processing unit with antialiasing

#76 | 2005-12-13
US10430629
-

System and method for generating multiple outputs in a single shader processing pass in a hardware graphics pipeline

#77 | 2005-11-22
US10658056
-

Antialiasing using hybrid supersampling-multisampling

#78 | 2005-10-11
US10302465
-

Programmable graphics system and method using flexible, high-precision data formats

#79 | 2005-02-08
US9687453
-

Controller for a memory system having multiple partitions

InventorID:

452911 ⎘