NVIDIA Corp.

SINGLE-VIEW BODY MESH LEARNING THROUGH ACCURATE DEPTH ESTIMATION

ADAPTIVE CLOCK GENERATION FOR SERIAL LINKS

TEXT-TO-IMAGE PRODUCT PLACEMENT

REVERSE-OFFLOAD OF TASKS BETWEEN DATA PROCESSORS

RESONATORS TO TRACK AND CONTROL MODE-LOCKED LASER DIODES

CLOCK STRETCHING CIRCUIT FOR MINIMUM OPERATING VOLTAGE IMPROVEMENT

PHYSICALLY UNCLONABLE FUNCTION CELLS WITH HOT CARRIER INJECTION

PUBLISH-SUBSCRIBE MECHANISM FOR PARALLEL MEMORY SYSTEM

ENERGY-BASED DIFFUSION LANGUAGE MODEL

GATED DELTA NETWORKS

FINE-GRAINED MIXED PRECISION FOR LARGE LANGUAGE MODEL INFERENCE

GENERATIVE ANIMATABLE GAUSSIAN AVATAR

INVERSE LITHOGRAPHY FOR HIGH QUALITY CURVY MASK GENERATION

HARDWARE CODE GENERATION FROM MULTIMEDIA SPECIFICATION DOCUMENTS

CONFIGURING A VISUAL LANGUAGE MODEL WITH SPATIAL UNDERSTANDING FOR ROBOTICS

SCENE-AWARE SPEECH RECOGNITION USING VISION-LANGUAGE MODELS

BIDIRECTIONAL MICRORING RESONATOR-BASED PHOTONIC LINK ARCHITECTURE

DYNAMIC PACKET COMPRESSION FOR TRANSMITTING NUMERICAL DATA

WIRE REDUCTION IN A HIGH PERFORMANCE INTERFACE

OBJECT-CENTRIC DIFFUSION POLICY FOR EFFICIENT IMITATION LEARNING

DIFFERENTIABLE EDGE-BASED OPTICAL PROXIMITY CORRECTION

HARDWARE ACCELERATOR FOR GAUSSIAN RENDERING AND RECONSTRUCTION

AVERAGE RATE REGULATOR FOR PARALLEL ADAPTIVE SAMPLER

JOINT IMAGE AND VIDEO TOKENIZATION WITH CAUSAL VARIATIONAL AUTOENCODER

DYNAMIC RING ASSIGNMENT FOR DENSE WAVE DIVISION MULTIPLEXING SYSTEMS

SILICON STRUCTURE TO MONITOR BITCELL PERFORMANCE

ANALOG RANDOM SEQUENCE GENERATORS

ADAPTIVE SLEW-RATE BOOSTER

ROBOT MOTION GENERATION ON ENHANCED COMPUTER PROCESSORS

FEED FORWARD SUPPLY NOISE CANCELLATION (FFNC) TECHNIQUE WITH LOAD CURRENT SENSOR FOR REGULATOR PSR IMPROVEMENT

LARGE LANGUAGE MODEL FOR STANDARD CELL LAYOUT DESIGN OPTIMIZATION

COOLER DETECTION AND ATTACH CHARACTERIZATION IN SYSTEM

THREE DIMENSIONAL GAUSSIAN SPLATTING WITH EXACT PERSPECTIVE TRANSFORMATION

TRANSMITTER-SIDE LINK TRAINING WITH IN-BAND HANDSHAKING

SILICON STRUCTURES TO MONITOR DEVICE CAPACITANCES

TRANSIENT CURRENT-MODE SIGNALING SCHEME FOR ON-CHIP INTERCONNECT FABRICS

REGION-AWARE VISION LANGUAGE PROCESSOR

SELF-SUPERVISED SPEECH QUALITY ESTIMATION AND ENHANCEMENT

CDMA OVER WDM AS A LINK MANAGEMENT PROTOCOL

CONTENTION-FREE DUAL-VOLTAGE LOGIC CELL

PHYSICALLY UNCLONABLE CELL WITH SINGLE TRANSISTOR TYPES TO IMPROVE VOLTAGE AND TEMPERATURE STABILITY

AERIAL IMAGE GENERATION THROUGH PHYSICS-INFORMED KERNEL LEARNING

THREE DIMENSIONAL CHIP AND PACKAGE INTEGRATION WITH BACKSIDE METALLIZATION

MECHANISMS FOR CONTROLLING CO-EXECUTION OF HETEROGENEOUS COOPERATIVE THREAD ARRAYS

OUTPUT LATCH AND AMPLIFIER

ALIAS-FREE DIFFUSION MODELS

CAPACITIVE NOISE COMPENSATION FOR A READ BITLINE IN A MACHINE MEMORY

SOFTWARE-DIRECTED DIVERGENT BRANCH TARGET PRIORITIZATION

CDMA OVER WDM FOR LIGHT SOURCE FREQUENCY LOCKING

LASER SPARING ARCHITECTURES FOR MULTI-WAVELENGTH LASER ARRAYS

LINE DRIVERS FOR LOW-VOLTAGE SIGNALING BETWEEN DIFFERENT VOLTAGE DOMAINS

DIFFERENTIABLE GLOBAL ROUTER

LEARNING-BASED PLACEMENT FOR CONGESTION MITIGATION

DATA-EFFICIENT DEMONSTRATION EXPANSION FOR TRAINING A GENERALIST ROBOTIC AGENT

PACKAGE LAYOUTS UTILIZING NON-RECTANGULAR PERIPHERAL CHIPS

ANTI-ALIASING SCOREBOARD MECHANISM TO MITIGATE EXECUTION DELAYS OF LONG-LATENCY INSTRUCTION EXECUTIONS

WIDE-RANGE POWER DELIVERY SYSTEM

CLOCK TO ANALOG REFERENCE VOLTAGE GENERATOR

MECHANISM FOR DETECTING AND MITIGATING CONGESTION IN A DRAGONFLY NETWORK

THREE DIMENSIONAL CIRCUIT MOUNTING STRUCTURES

BACKLIGHT-FREE AUGMENTED REALITY USING DIGITAL HOLOGRAPHY

DYNAMIC STANDARD CELL EXTERNAL PIN METHODOLOGY FOR ROUTABILITY-DRIVEN STANDARD CELL DESIGN AUTOMATION

PIN DENSITY-BASED CONGESTION ESTIMATION FOR ROUTABILITY-DRIVEN STANDARD CELL SYNTHESIS

VOLTAGE REGULATOR DROOP REDUCTION MECHANISM

BIDIRECTIONAL MICRORING RESONATOR-BASED PHOTONIC LINK ARCHITECTURE

FERROMAGNETIC MATERIAL BASED INTEGRATED INDUCTOR IN SILICON

LOGIC CELL PLACEMENT MECHANISMS FOR IMPROVED CLOCK ON-CHIP VARIATION

VIA-BASED INDUCTOR COIL FOR INTEGRATED SILICON APPLICATIONS

DIGITALLY CONTROLLED UNIFIED RECEIVER FOR MULTI-RANK SYSTEM

DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE

LOW-PRECISION FLOATING-POINT DATAPATH IN A COMPUTER PROCESSOR

LEVEL-CONVERSION CIRCUITS FOR SIGNALING ACROSS VOLTAGE DOMAINS

LARGE SCALE MASK OPTIMIZATION WITH CONVOLUTIONAL FOURIER NEURAL OPERATOR AND LITHO-GUIDED SELF LEARNING