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Inventor profile of:

Bernhard Egger

City:

Seoul

Country:

South Korea

Published Applications:

42

Last publication date:

2026-04-30

Top Assignees for applications by Bernhard Egger

The entities that hold a legal rights for patent applications filed by inventor Egger Bernhard:

SAMSUNG ELECTRONICS CO., LTD. 37 Suwon-si, South Korea
Seoul National University R&DB Foundation 12 Seoul, South Korea
SAMSUNG ELECTRONICS CO., LTD. 3 Gyeonggi-Do, South Korea
SNU R&DB FOUNDATION 3 Seoul, South Korea
Seoul National University R&DB Foundation 1 , South Korea
SAMSUNG ELECTRONICS CO. LTD. 1 Suwon-si, Gyeonggi-do, South Korea
Samsung Electronics Co., Ltd 1 , South Korea
Postech Academy-Industry Foundation 1 Pohang-si, South Korea
Seoul Electronics University R&DB Foundation 1 Seoul, South Korea

Recent patent applications by Egger Bernhard

Bernhard Egger from Seoul, KR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-30

US20260119175A1

MEMORY DEVICE AND METHOD

#2 | 2024-06-20

US20240202527A1

METHOD AND APPARATUS WITH NEURAL NETWORK OPTIMIZATION

#3 | 2024-06-13

US20240193406A1

METHOD AND APPARATUS WITH SCHEDULING NEURAL NETWORK

#4 | 2024-06-06

US20240185077A1

APPARATUS AND METHOD WITH QUANTIZATION CONFIGURATOR

#5 | 2023-06-22

US20230195439A1

Apparatus and method with neural network computation scheduling

#6 | 2021-09-09

US20210279587A1

METHOD AND APPARATUS FOR NEURAL NETWORK CODE GENERATION

#7 | 2019-11-07

US20190339760A1

Computing devices and methods of allocating power to plurality of cores in each computing device

#8 | 2018-08-30

US20180246554A1

Computing devices and methods of allocating power to plurality of cores in each computing device

#9 | 2018-06-28

US20180181443A1

Method of processing OpenCL kernel and computing device therefor

#10 | 2018-03-08

US20180067895A1

Electronic device, reconfigurable processor and controlling methods thereof

#11 | 2017-09-28

US20170277571A1

Multi-core processor and method of controlling the same using revisable translation tables

#12 | 2014-05-29

US20140149968A1

Dynamic library profiling method and dynamic library profiling system

#13 | 2014-05-29

US20140149078A1

PERFORMANCE MEASUREMENT UNIT, PROCESSOR CORE INCLUDING THE SAME AND PROCESS PROFILING METHOD

#14 | 2014-03-13

US20140075253A1

Method for verification of reconfigurable processor

#15 | 2014-02-20

US20140052960A1

Apparatus and method for generating VLIW, and processor and method for processing VLIW

#16 | 2013-09-26

US20130254517A1

Apparatus and method for processing invalid operation in prologue or epilogue of loop

#17 | 2012-08-09

US20120204001A1

Reconfigurable processor with routing node frequency based on the number of routing nodes

#18 | 2012-07-19

US20120185673A1

Reconfigurable processor using power gating, compiler and compiling method thereof

#19 | 2012-06-21

US20120159114A1

Register file and computing device using the same

#20 | 2012-06-07

US20120144399A1

APPARATUS AND METHOD FOR SYNCHRONIZATION OF THREADS

#21 | 2012-05-17

US20120124351A1

Apparatus and method for dynamically determining execution mode of reconfigurable array

#22 | 2012-04-26

US20120102496A1

Reconfigurable processor and method for processing a nested loop

#23 | 2012-04-19

US20120096247A1

Reconfigurable processor and method for processing loop having memory dependency

#24 | 2012-04-12

US20120089823A1

PROCESSING APPARATUS, COMPILING APPARATUS, AND DYNAMIC CONDITIONAL BRANCH PROCESSING METHOD

#25 | 2012-04-12

US20120089821A1

Debugging apparatus and method

#26 | 2012-04-12

US20120089813A1

COMPUTING APPARATUS BASED ON RECONFIGURABLE ARCHITECTURE AND MEMORY DEPENDENCE CORRECTION METHOD THEREOF

#27 | 2012-04-12

US20120089808A1

Multiprocessor using a shared virtual memory and method of generating a translation table

#28 | 2012-03-01

US20120054468A1

PROCESSOR, APPARATUS, AND METHOD FOR MEMORY MANAGEMENT

#29 | 2011-09-29

US20110238963A1

Analyzing data flow graph to detect data for copying from central register file to local register file used in different execution modes in reconfigurable processing array

#30 | 2011-09-29

US20110238945A1

Apparatus and method for generating code overlay

#31 | 2011-09-22

US20110231635A1

Register, processor, and method of controlling a processor using data type information

#32 | 2011-09-22

US20110231627A1

Memory managing apparatus and method using a pointer indicator bit to perform garbage collection

#33 | 2011-09-15

US20110225399A1

PROCESSOR AND METHOD FOR SUPPORTING MULTIPLE INPUT MULTIPLE OUTPUT OPERATION

#34 | 2011-08-18

US20110202749A1

NOP instruction compressing apparatus and method in a VLIW machine

#35 | 2010-10-28

US20100274939A1

Reconfigurable processor with designated processing elements and reserved portion of register file for interrupt processing

#36 | 2010-09-02

US20100223449A1

Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus

#37 | 2010-08-19

US20100211759A1

Apparatus and method for generating VLIW, and processor and method for processing VLIW

#38 | 2010-08-05

US20100199076A1

Computing apparatus and method of handling interrupt

#39 | 2010-08-05

US20100199069A1

Scheduler of reconfigurable array, method of scheduling commands, and computing apparatus

#40 | 2010-08-05

US20100199068A1

Reconfigurable processor with pointers to configuration information and entry in NOP register at respective cycle to deactivate configuration memory for reduced power consumption

#41 | 2010-07-22

US20100185839A1

Apparatus and method for scheduling instruction

#42 | 2010-07-08

US20100174885A1

Reconfigurable processor with predicate signal activated operation configuration memory and separate routing configuration memory

InventorID:

459662 ⎘