Michael A. Filippo

Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy

Controlling writes to non-renamed register space in an out-of-order execution microprocessor

System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor

Speculation pointers to identify data-speculative operations in microprocessor

Cache memory subsystem including a fixed latency R/W pipeline

Load store unit with replay mechanism

Processor with dependence mechanism to predict whether a load is dependent on older store

Clock control of functional units in an integrated circuit based on monitoring unit signals to predict inactivity

Apparatus and method for decreasing power consumption in an integrated circuit

Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor

System and method for handling exceptional instructions in a trace cache based processor

Store-to-load forwarding buffer using indexed lookup