Dmitri E. Nikonov

Diode connected non-linear input capacitors based majority gate

TRANSISTOR DEVICES WITH PEROVSKITE FILMS

FINE-GRAINED DISAGGREGATED SERVER ARCHITECTURE

Magnetoelectric inverter

Magnetoelectric majority gate device

Magnetoelectric XNOR logic gate device

BINARY-WEIGHTED CAPACITOR CHARGE-SHARING FOR MULTIPLICATION

Three-dimensional oscillator structure

Cross-point magnetic random access memory with piezoelectric selector

Probabilistic in-memory computing

Multi-level spin logic

Precise writing of multi-level weights to memory devices for compute-in-memory

Macro storage cell composed of multiple storage devices each capable of storing more than two states

Magnetic memory device with ruthenium diffusion barrier

Neural computing dies with stacked neural core regions

Staged oscillators for neural computing

Cross-point magnetic random access memory with piezoelectric selector

Techniques for forming vias and other interconnects for integrated circuit structures

Perpendicular magnetoelectric spin orbit logic

Magnetic contacts for spin qubits

PIEZORESISTIVE SELF-OSCILLATOR

Wireless oscillator neural network

Semiconductor devices with metal contacts including crystalline alloys

Three-dimensional oscillator structure

Circuits based on magnetoelectric transistor devices

Multi-level spin logic

Magnetoelectric spin orbit logic with paramagnets

Quaternary spin hall memory

Magneto-electric spin orbit (MESO) structures having functional oxide vias

Magnetostrictive stack and corresponding bit-cell

Transistors with metal source and drain contacts including a Heusler alloy

FOUR STABLE STATE NEURON

Magnetic and spin logic devices based on Jahn-Teller materials

Nonvolatile SRAM

Spin logic with magnetic insulators switched by spin orbit coupling

Magneto-electric logic devices using semiconductor channel with large spin-orbit coupling

Spin logic with spin hall electrodes and charge interconnects

Metallic spin super lattice for logic and memory devices

Spin logic device with high spin injection efficiency from a matched spin transfer layer

Magnetoelectric memory cells with domain-wall-mediated switching

Strain assisted spin torque switching spin transfer torque memory

Spin-orbit logic with charge interconnects and magnetoelectric nodes

Coupled spin hall nano oscillators with tunable strength

Magnetic nanomechanical devices for stiction compensation

Magnetic state element and circuits

Non-boolean associative processor degree of match and winner take all circuits

Magnetic domain wall logic devices and interconnect

Tunneling field effect transistors with a variable bandgap channel

Self-storing and self-restoring non-volatile static random access memory

Clocked all-spin logic circuit

Apparatus and method to optimize STT-MRAM size and write error rate

Nanomagnetic devices switched with a spin hall effect

Spintronic logic element

Non-volatile latch using magneto-electric and ferro-electric tunnel junctions

Reduced scale resonant tunneling field effect transistor

Spin torque oscillator having multiple fixed ferromagnetic layers or multiple free ferromagnetic layers

Magnetic element for memory and logic

High speed precessionally switched magnetic logic

MAGNETIC SHIELDED INTEGRATED CIRCUIT PACKAGE

Magnetic state element and circuits

High speed precessionally switched magnetic logic

Micromagnet Based Extreme Ultra-Violet Radiation Source

Cross point array MRAM having spin hall MTJ devices

Integrated capacitor based power distribution

Magnetic state element and circuits

Semiconductor package with optical port

Integrated circuits and systems and methods for producing the same

Transparent holographic display with dynamic image control

Methods and apparatus for modeling and simulating spintronic integrated circuits

High speed precessionally switched magnetic logic

Associative memory oscillator array

Methods of forming spin torque devices and structures formed thereby