Inventor profile of:

Satheesh Chellappan

City:

Folsom, California

Country:

United States

Published Applications:

28

Last publication date:

2024-08-22

Top Assignees for applications by Satheesh Chellappan

The entities that hold a legal rights for patent applications filed by inventor Chellappan Satheesh:

Recent patent applications by Chellappan Satheesh

Satheesh Chellappan from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-08-22
US20240281196A1
Physics

CONTROL AND MEMORY ACCESSES USING STREAMING AUDIO

#2 | 2023-05-25
US20230161723A1
Physics

ROLE DETECTION FOR USB-BASED CHARGING

#3 | 2022-10-06
US20220317855A1
Physics

METHODS AND APPARATUS TO PROCESS TOUCH DATA

#4 | 2022-07-07
US20220217099A1
Electricity

VIRTUAL PHYSICAL CIRCUIT FOR ON-CHIP COMMUNICATION

#5 | 2022-06-09
US20220179821A1
Physics

HARDWARE AND PROTOCOLS TO SUPPORT IMAGE TRANSFERS OVER MIPI I2C/I3C BUSES

#6 | 2022-05-26
US20220164130A1
Physics

METHOD AND SYSTEM OF STANDARDS-BASED AUDIO FUNCTION PROCESSING WITH REDUCED MEMORY USAGE

#7 | 2022-04-14
US20220113758A1
Physics

SELECTABLE CLOCK SOURCES

#8 | 2021-08-26
US20210266610A1
Electricity

Methods and apparatus to reduce audio streaming latency between audio and gigabit ethernet subsystems

#9 | 2019-05-23
US20190158890A1
Electricity

Methods and apparatus to reduce audio streaming latency between audio and Gigabit Ethernet subsystems

#10 | 2019-05-23
US20190155371A1
Physics

Low power data processing offload using external platform component

#11 | 2019-05-09
US20190139399A1
Physics

Methods, systems and apparatus to use audio return path for functional safety validation

#12 | 2019-04-04
US20190101592A1
Physics

Systems and methods for bypass testing

#13 | 2019-02-07
US20190042483A1
Physics

Methods and apparatus to offload media streams in host devices

#14 | 2019-01-17
US20190018802A1
Physics

USB2 high speed connection for testing

#15 | 2018-10-04
US20180285310A1
Physics

Device, system and method for packet processing to facilitate circuit testing

#16 | 2018-07-05
US20180188321A1
Physics

Device, system and method for providing on-chip test/debug functionality

#17 | 2018-06-28
US20180181371A1
Physics

DATA THROTTLING FOR HIGH SPEED COMPUTING DEVICES

#18 | 2018-04-05
US20180096736A1
Physics

High speed I/O pinless structural testing

#19 | 2018-01-04
US20180004685A1
Physics

Efficient low cost on-die configurable bridge controller

#20 | 2017-10-05
US20170286357A1
Physics

Method, Apparatus And System For Communicating Between Multiple Protocols

#21 | 2017-06-29
US20170185550A1
Physics

Configuration arbiter for multiple controllers sharing a link interface

#22 | 2017-06-22
US20170176534A1
Physics

SELF-CHARACTERIZING HIGH-SPEED COMMUNICATION INTERFACES

#23 | 2017-03-09
US20170070381A1
Electricity

Override subsystems for rapid recovery from serial-link errors

#24 | 2016-09-29
US20160283434A1
Physics

Apparatus, system and method for sharing physical layer logic across multiple protocols

#25 | 2015-07-30
US20150212969A1
Physics

Configuring a remote M-PHY

#26 | 2015-05-14
US20150134866A1
Physics

Inter-chip communications with link layer interface and protocol adaptor

#27 | 2013-11-07
US20130297833A1
Physics

Configuring a remote M-PHY

#28 | 2013-10-03
US20130262731A1
Physics

Superspeed inter-chip interface

InventorID:

471395 ⎘