SANJEEV GHAI

Prefetch unit filter for microprocessor

Accelerated processing of streams of load-reserve requests

Synchronized access to data in shared memory by protecting the load target address of a fronting load

Information handling system with immediate scheduling of load operations

Synchronized access to shared memory by extending protection for a store target address of a store-conditional request

Dynamic transaction throttling in a data processing system supporting transactional memory

SYNCHRONIZED ACCESS TO DATA IN SHARED MEMORY BY PROTECTING THE LOAD TARGET ADDRESS OF A FRONTING LOAD

Temporarily favoring selection of store requests from one of multiple store queues for issuance to a bank of a banked cache

Banked cache temporarily favoring selection of store requests from one of multiple store queues

Memory move instruction sequence including a stream of copy-type and paste-type instructions

Memory access in a data processing system utilizing copy and paste instructions

Injection of at least a partial cache line in a private multilevel cache hierarchy

Bypassing a store-conditional request around a store queue

Bypassing a store-conditional request around a store queue

Techniques for logging addresses of high-availability data via a non-blocking channel

Logging addresses of high-availability data

Cache configured to log addresses of high-availability data via a non-blocking channel

Cache configured to log addresses of high-availability data

Management of transactional memory access requests by a cache memory

Protecting the footprint of memory transactions from victimization

PROTECTING THE FOOTPRINT OF MEMORY TRANSACTIONS FROM VICTIMIZATION

Management of transactional memory access requests by a cache memory

Virtual machine failover

Virtual machines failover

Data cache block deallocate requests in a multi-level cache hierarchy

Data cache block deallocate requests

Data cache block deallocate requests in a multi-level cache hierarchy

Data cache block deallocate requests

Information handling system with immediate scheduling of load operations

Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow

Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow

Information handling system with immediate scheduling of load operations and fine-grained access to cache memory

Double DRAM bit steering for multiple error corrections

Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices

Data processing system and method for handling castout collisions

Efficient storage of metadata in a system memory

DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING CONTROLLABLE STORE GATHER WINDOWS

Double DRAM bit steering for multiple error corrections

Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices

Data processing system and method for efficient storage of metadata in a system memory

Data processing system and method for handling castout collisions

Adaptive memory access speculation

Data processing system having no system memory

Data processing system and method of communication that employ a request-and-forget protocol

Method and system of managing virtualized physical memory in a data processing system

Method and system for thread-based memory speculation in a memory subsystem of a data processing system

Method and system for supplier-based memory speculation in a memory subsystem of a data processing system

Method and system of managing virtualized physical memory in a memory controller and processor system

Method and system of managing virtualized physical memory in a multi-processor system

Data processing system having a physically addressed cache of disk memory