Muhammad M. Khellah

BALANCED STATIC RANDOM-ACCESS MEMORY (SRAM)

STATIC RANDOM-ACCESS MEMORY

SYSTEMS AND METHODS THAT INCLUDE STANDARD CELL YIELD PREDICTIONS IN A LIBRARY

TECHNIQUES TO UTILIZE NEAR MEMORY COMPUTE CIRCUITRY FOR MEMORY-BOUND WORKLOADS

N-P BALANCED MULTI-PORT REGISTER FILE WITH COMPLEMENTARY FIELD-EFFECT TRANSISTORS (CFETS)

THREE-TRANSISTOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY GAIN CELL IN COMPLEMENTARY FIELD EFFECT TRANSISTOR PROCESS

MULTI-PORTED REGISTER FILE WITH CFETS

SRAM WITH P-TYPE ACCESS TRANSISTORS AND COMPLEMENTARY FIELD-EFFECT TRANSISTOR TECHNOLOGY

POWER MANAGEMENT FOR EXECUTION OF MACHINE LEARNING WORKLOADS

Concurrent compute and ECC for in-memory matrix vector operations

Techniques for multi-read and multi-write of memory circuit

Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators

Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagation

Method and apparatus for switched adaptive clocking

NEAREST NEIGHBOR SEARCH LOGIC CIRCUIT WITH REDUCED LATENCY AND POWER CONSUMPTION

NVRAM SYSTEM MEMORY WITH MEMORY SIDE CACHE THAT FAVORS WRITTEN TO ITEMS AND/OR INCLUDES REGIONS WITH CUSTOMIZED TEMPERATURE INDUCED SPEED SETTINGS

Multi-bit pulsed latch including serial scan chain

Low swing bitline for sensing arrays

Techniques for multi-read and multi-write of memory circuit

Apparatus, video processing unit and method for clustering events in a content addressable memory

Aging aware dynamic keeper apparatus and associated method

Post synaptic potential-based learning rule

Low swing bitline for sensing arrays

Bi-directional multi-mode charge pump

Voltage level shifter monitor with tunable voltage level shifter replica circuit

Flip-flop circuit with low-leakage transistors

Power switching circuitry including power-up control

Pre-synaptic learning using delayed causal updates

Hybrid compression scheme for efficient storage of synaptic weights in hardware neuromorphic cores

Disabling cache portions during low voltage operations

Apparatus for data retention and supply noise mitigation using clamps

Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions

Graphics processor sub-domain voltage regulation

Bi-directional multi-mode charge pump

Technologies for memory management of neural networks with sparse connectivity

Apparatus for data retention and supply noise mitigation using clamps

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions

Memory cell with improved write margin

Apparatus and method for reducing during power wake-up

Voltage level shifter circuit

Current steering level shifter

Voltage level shifter circuit

Apparatus for reducing write minimum supply voltage for memory

Apparatus for adjusting supply level to improve write margin of a memory cell

Apparatus for dual purpose charge pump

Graphics processor sub-domain voltage regulation

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators

Disabling cache portions during low voltage operations

Memory cell with improved write margin

Apparatus for reducing write minimum supply voltage for memory

Circuits and methods for reducing minimum supply for register file cells

Method of correcting adjacent errors by using BCH-based error correction coding

Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states

Disabling cache portions during low voltage operations

Memory write operation methods and circuits

MEMORY ARRAY HAVING EXTENDED WRITE OPERATION

Method and system to lower the minimum operating voltage of a memory array

Disabling cache portions during low voltage operations

Leakage compensation circuit for Dynamic Random Access Memory (DRAM) cells

Reducing minimum operating voltage through hybrid cache design

MEMORY CIRCUIT WITH ECC BASED WRITEBACK

Sense amplifier method and arrangement

Address hashing to help distribute accesses across portions of destructive read cache memory

Memory having bit line with resistor(s) between memory cells

Memory driver circuits with embedded level shifters

Low power serial link bus architecture

Dual gate oxide one time programmable (OTP) antifuse cell

Memory cell having p-type pass device

Capacitor structure for a logic process

Operating an information storage cell array

Memory circuit

Memory cell driver circuits

Apparatus and method for programming a memory array

Purge-based floating body memory

Memory with dynamically adjustable supply

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Reducing power consumption in integrated circuits

2-transistor floating-body dram

Representative majority voter for bus invert coding

One time programmable memory

Memory circuit

Floating-body dynamic random access memory with purge line

OTP antifuse cell and cell array

Non volatile data storage through dielectric breakdown

Crosspoint memory array utilizing one time programmable antifuse cells

Apparatus and method for a one-phase write to a one-transistor memory cell array

Floating-body memory cell write

SRAM cell power reduction circuit

Majority voter apparatus, systems, and methods

Memory cell without halo implant

Asymmetric memory cell

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Two transistor gain cell, method, and system

Interconnect structure in integrated circuits

Overvoltage detection apparatus, method, and system

SRAM with forward body biasing to improve read cell stability

Bit-line droop reduction

Asymmetric memory cell