Boise, Idaho
United States
20
2022-01-13
The entities that hold a legal rights for patent applications filed by inventor Schrinsky Alex J.:
Alex J. Schrinsky from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Microelectronic devices having features with a fin portion of different sidewall slope than a lower portion, and related methods and electronic systems
#2 | 2021-01-07Integrated circuitry, arrays of capacitors of integrated circuitry, and methods used in the fabrication of integrated circuitry
#3 | 2020-12-31Apparatus with doped surfaces, and related methods with in situ doping
#4 | 2020-09-10Integrated assemblies having dielectric regions along conductive structures, and methods of forming integrated assemblies
#5 | 2020-07-30FORMATION OF A TRENCH USING A POLYMERIZING RADICAL MATERIAL
#6 | 2019-12-12Integrated assemblies having dielectric regions along conductive structures, and methods of forming integrated assemblies
#7 | 2019-07-09Methods of forming integrated assemblies having dielectric regions along conductive structures
#8 | 2018-01-18Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
#9 | 2017-09-05Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
#10 | 2016-01-07Semiconductor constructions having peripheral regions with spaced apart mesas
#11 | 2015-11-26METHOD FOR A DRY EXHUMATION WITHOUT OXIDATION OF A CELL AND SOURCE LINE
#12 | 2014-10-16Semiconductor constructions
#13 | 2013-10-10Use of etch process post wordline definition to improve data retention in a flash memory device
#14 | 2011-06-30Methods of forming electrically insulative materials, methods of forming low k dielectric regions, and methods of forming semiconductor constructions
#15 | 2010-11-18Methods of forming patterns on substrates
#16 | 2010-05-13Methods of forming electrically insulative materials, methods of forming low k dielectric regions, and methods of forming semiconductor constructions
#17 | 2009-04-09Semiconductor constructions having multiple patterned masking layers over NAND gate stacks
#18 | 2008-07-17Methods of forming NAND cell units with string gates of various widths
#19 | 2006-08-24Method of forming a conductive line and a method of forming a conductive contact adjacent to and insulated from a conductive line
#20 | 2006-02-23Methods of forming conductive lines
474147 ⎘