Barcelona
Spain
25
2025-04-03
The entities that hold a legal rights for patent applications filed by inventor Lupon Marc:
Marc Lupon from Barcelona, ES has applied for patents for these inventions. The list has both pending applications and granted patents:
METHOD AND APPARATUS FOR DISTRIBUTED AND COOPERATIVE COMPUTATION IN ARTIFICIAL NEURAL NETWORKS
#2 | 2023-01-19METHOD AND APPARATUS FOR DISTRIBUTED AND COOPERATIVE COMPUTATION IN ARTIFICIAL NEURAL NETWORKS
#3 | 2021-10-21Method and apparatus for distributed and cooperative computation in artificial neural networks
#4 | 2019-01-03PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY
#5 | 2018-12-06Reconfigurable processing unit
#6 | 2018-11-15Processing device for performing convolution operations
#7 | 2017-09-28Method and apparatus for distributed and cooperative computation in artificial neural networks
#8 | 2017-08-03Processing device for performing convolution operations
#9 | 2017-02-09Double rounded combined floating-point multiply and add
#10 | 2016-06-23Storage device and method for performing convolution operations
#11 | 2016-03-31Instruction and logic for bulk register reclamation
#12 | 2016-03-17Double rounded combined floating-point multiply and add
#13 | 2016-01-28WEIGHT-SHIFTING MECHANISM FOR CONVOLUTIONAL NEURAL NETWORKS
#14 | 2015-06-25Processing device for performing convolution operations
#15 | 2015-06-18Reconfigurable processing unit
#16 | 2015-01-22Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs
#17 | 2015-01-01Partial commits in dynamic binary translation based systems
#18 | 2014-09-18Combined floating point multiplier adder with intermediate rounding logic
#19 | 2014-06-05METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT INSTRUCTION
#20 | 2014-04-03Instruction and logic for optimization level aware branch prediction
#21 | 2014-01-16Managed instruction cache prefetching
#22 | 2014-01-02Double rounded combined floating-point multiply and add
#23 | 2013-12-12Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region
#24 | 2013-12-05METHOD AND APPARATUS FOR CONTROLLING A MXCSR
#25 | 2013-10-10SUPPORT FOR SPECULATIVE OWNERSHIP WITHOUT DATA
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