Haifa
Israel
25
2026-03-12
The entities that hold a legal rights for patent applications filed by inventor Natanzon Esfir:
Esfir Natanzon from Haifa, IL has applied for patents for these inventions. The list has both pending applications and granted patents:
APPLICATION PRIORITY BASED POWER MANAGEMENT FOR A COMPUTER DEVICE
#2 | 2024-07-11APPLICATION PRIORITY BASED POWER MANAGEMENT FOR A COMPUTER DEVICE
#3 | 2024-04-25APPLICATION PRIORITY BASED POWER MANAGEMENT FOR A COMPUTER DEVICE
#4 | 2023-12-28DEVICE, METHOD AND SYSTEM FOR TRANSPARENTLY CHANGING A FREQUENCY OF AN INTERCONNECT FABRIC
#5 | 2022-06-09Device, method and system for transparently changing a frequency of an interconnect fabric
#6 | 2021-06-24Application priority based power management for a computer device
#7 | 2020-07-02Controlling power state demotion in a processor
#8 | 2020-06-04Hardware unit for controlling operating frequency in a processor
#9 | 2019-07-04System, apparatus and method for controlling a processor based on effective stress information
#10 | 2019-06-27System, apparatus and method for processor-external override of hardware performance state control of a processor
#11 | 2018-05-03Forcing a processor into a low power state
#12 | 2018-03-01Method and apparatus for automatic adaptive voltage control
#13 | 2017-05-11METHOD AND APPARATUS FOR PERFORMANCE EFFICIENT ISA VIRTUALIZATION USING DYNAMIC PARTIAL BINARY TRANSLATION
#14 | 2017-01-19CPU/GPU synchronization mechanism
#15 | 2016-06-02Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation
#16 | 2016-05-26Controlling a guaranteed frequency of a processor
#17 | 2016-03-10Providing lifetime statistical information for a processor
#18 | 2015-12-31Apparatus and method for a user configurable reliability control loop
#19 | 2015-12-24Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation
#20 | 2015-12-10Forcing a processor into a low power state
#21 | 2014-04-03Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation
#22 | 2014-01-16BINARY TRANSLATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM
#23 | 2013-10-10Core switching acceleration in asymmetric multiprocessor system
#24 | 2012-09-20Page Fault Handling Mechanism
#25 | 2012-09-13Implementing TLB Synchronization for Systems with Shared Virtual Memory Between Processing Devices
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