Eric R. Keller

Method for scheduling a network packet processor

Method for message processing on a programmable logic device

Generation of executable threads having source code specifications that describe network packets

Pipeline for processing network packets

Thread circuits and a broadcast channel in programmable logic

Method for simulating a processor of network packets

Circuit for modification of a network packet by insertion or removal of a data segment

Generation of a specification of a network packet processor

Method and apparatus for multithreading on a programmable logic device

Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element

Bootable integrated circuit device for readback encoding of configuration data

Memory arrangement for message processing by a plurality of threads

Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip

Method for message processing on a programmable logic device

Using redundant routing to reduce susceptibility to single event upsets in PLD designs

Bootable programmable logic device for internal decoding of encoded configuration data

Method and apparatus for a programmable interface of a soft platform on a programmable logic device

Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip

Using an embedded processor to implement a finite state machine

Methods of reducing the susceptibility of PLD designs to single event upsets

Method of and apparatus for enabling a hardware module to interact with a data structure

Method of using a hardware library in a programmable logic device

Configurable address generator and circuit using same

Reconfiguration of a programmable logic device using internal control

Reconfiguration of a programmable logic device using internal control

Method and system for generating a circuit design including a peripheral component connected to a bus