Jonathan D. Combs

METHODS, SYSTEMS, AND APPARATUSES FOR VARIABLE WIDTH UNALIGNED FETCH IN A PROCESSOR

BRANCH TYPE LOGGING IN LAST BRANCH REGISTERS

BRANCH TYPE LOGGING IN LAST BRANCH REGISTERS

Branch type logging in last branch registers

System and method for load balancing in out-of-order clustered decoding

Monitoring performance of a processing device to manage non-precise events

Apparatuses, methods, and systems for memory disambiguation

System and Method for Out-of-Order Clustered Decoding

Method and apparatus for processor performance monitoring

Monitoring performance of a processing device to manage non-precise events

Loop streaming detector for standard and complex instruction types

Context control and parameter passing within microcode based instruction routines

Sharing TLB mappings between contexts

Physical register table for eliminating move instructions

Flag non-modification extension for ISA instructions using prefixes

Conditional execution support for ISA instructions using prefixes

Enhanced microcode address stack pointer manipulation

Programmable logic array and read-only memory area reduction using context-sensitive logic for data space manipulation

INDIRECT BRANCH PREDICTION BASED ON BRANCH TARGET BUFFER HYSTERESIS

Aliased Parameter Passing Between Microcode Callers and Microcode Subroutines

Saving Values Corresponding to Parameters Passed Between Microcode Callers and Microcode Subroutines from Microcode Alias Locations to a Destination Storage Location

Method to remove stale branch predictions for an instruction prior to execution within a microprocessor

Associating address space identifiers with active contexts

Flag value renaming