Elpida Memory, Inc.

Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system

Semiconductor device having bit lines hierarchically structured

Semiconductor device and method of controlling the same

Semiconductor device having plurality of wiring layers and designing method thereof

VARIABLE RESISTIVE ELEMENT, AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

Semiconductor device including stacked semiconductor chips

Semiconductor device having counter circuit

Semiconductor device having penetration electrode penetrating through semiconductor substrate

Semiconductor device and manufacturing method thereof

Semiconductor device and information processing system including the same

DEVICE

SEMICONDUCTOR DEVICE INCLUDING ROW CACHE REGISTER

Method of manufacturing semiconductor device

Semiconductor memory device

Semiconductor device having ODT function

Semiconductor device having multi-level wiring structure

Semiconductor device that can adjust propagation time of internal clock signal

Semiconductor device having data output circuit in which slew rate thereof is adjustable

Semiconductor device having potential monitoring terminal to monitor potential of power-supply line

SEMICONDUCTOR DEVICE HAVING COMMAND MONITOR CIRCUIT

Semiconductor chip having plural penetration electrode penetrating therethrough

Semiconductor device

SEMICONDUCTOR DEVICE

Semiconductor device having hierarchical bit line structure

Semiconductor device having data terminal supplied with plural write data in serial

Semiconductor device and manufacturing method thereof

Method for fabricating a DRAM capacitor

Semiconductor device

SEMICONDUCTOR DEVICE INCLUDING CAPACITOR STABILIZING VARIATION OF POWER SUPPLY VOLTAGE

SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS

Semiconductor device having plural semiconductor chip stacked with one another

SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE

Semiconductor device

Semiconductor device including stacked semiconductor chips without occurring of crack

Semiconductor device and method for manufacturing the same

High performance dielectric stack for DRAM capacitor

Semiconductor device having skew detection circuit measuring skew between clock signal and data strobe signal

Semiconductor device

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

WAFER OR CIRCUIT BOARD AND JOINING STRUCTURE OF WAFER OR CIRCUIT BOARD

MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND COMMAND ADDRESS REGISTER BUFFER

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS STACKED ONE ANOTHER

Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device

Memory module including plural memory devices and data register buffer

Internal power supply circuit, semiconductor device, and manufacturing method of semiconductor device

Semiconductor device and information processing system including the same

SEMICONDUCTOR DEVICE

Semiconductor device having wiring pad and wiring formed on the same wiring layer

Semiconductor device

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Semiconductor device and manufacturing method thereof

SEMICONDUCTOR DEVICE INCLUDING SHARED PILLAR LOWER DIFFUSION LAYER

SEMICONDUCTOR CHIP HAVING PLURAL PENETRATING ELECTRODES THAT PENETRATE THERETHROUGH

Control method for a semiconductor memory device

Device having electrodes formed from bumps with different diameters

Semiconductor device and method of forming the same

Blocking layers for leakage current reduction in DRAM devices

SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS STACKED TO ONE ANOTHER

System with controller and memory

Method for manufacturing semiconductor device

Top electrode templating for DRAM capacitor

SEMICONDUCTOR DEVICE OPERATING ACCORDING TO LATENCY VALUE

Semiconductor device having plural selection lines selected based on address signal

Semiconductor device performing refresh operation

Memory device, semiconductor memory device and control method thereof

SEMICONDUCTOR DEVICE

DEVICE AND DATA PROCESSING SYSTEM

METHODS OF MANUFACTURING VARIABLE RESISTANCE MEMORY AND SEMICONDUCTOR DEVICE

Semiconductor device having latency counter to control output timing of data and data processing system including the same

Semiconductor device having a control chip stacked with a controlled chip

Device

Semiconductor device and stacked semiconductor device

Asymmetric MIM capacitor for DRAM devices

Layout data creation device for creating layout data of pillar-type transistor

SEMICONDUCTOR DEVICE INCLUDING DUMMY PILLAR NEAR INTERMEDIATE PORTION OF SEMICONDUCTOR PILLAR GROUP

Semiconductor device performing burst order control and data bus inversion

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor memory device and semiconductor device

Semiconductor device including output circuit constituted of plural unit buffer circuits in which impedance thereof are adjustable

Semiconductor device having impedance calibration function to data output buffer and semiconductor module having the same

Semiconductor device having input receiver circuit that operates in response to strobe signal

Logic circuit performing exclusive or operation and data processing system including the same

Semiconductor device and memory system

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE

SEMICONDUCTOR DEVICE

Electrode Treatments for Enhanced DRAM Performance

Electrode Treatments for Enhanced DRAM Performance

Semiconductor device having hierarchically structured bit lines and system including the same

Molybdenum oxide top electrode for DRAM capacitors

CAPACITOR INSULATING FILM, METHOD OF FORMING THE SAME, CAPACITOR AND SEMICONDUCTOR DEVICE USING THE CAPACITOR INSULATING FILM

Semiconductor device

Semiconductor device and semiconductor memory device

SEMICONDUCTOR MEMORY DEVICE HAVING DIODE CELL STRUCTURE

Semiconductor device

Semiconductor device

Bandgap reference circuit and method of starting bandgap reference circuit