Inventor profile of:

Ibrahim Ban

City:

Beaverton, Oregon

Country:

United States

Published Applications:

42

Last publication date:

2024-07-04

Top Assignees for applications by Ibrahim Ban

The entities that hold a legal rights for patent applications filed by inventor Ban Ibrahim:

Recent patent applications by Ban Ibrahim

Ibrahim Ban from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-07-04
US20240222440A1
Electricity

TRANSISTOR WITH A BODY AND BACK GATE STRUCTURE IN DIFFERENT MATERIAL LAYERS

#2 | 2024-06-27
US20240213140A1
Electricity

INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE HIGH

#3 | 2023-03-02
US20230069054A1
Electricity

GALLIUM NITRIDE (GAN) INTEGRATED CIRCUIT TECHNOLOGY WITH MULTI-LAYER EPITAXY AND LAYER TRANSFER

#4 | 2023-02-23
US20230054719A1
Electricity

GALLIUM NITRIDE (GAN) LAYER TRANSFER AND REGROWTH FOR INTEGRATED CIRCUIT TECHNOLOGY

#5 | 2022-12-29
US20220415894A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#6 | 2022-03-24
US20220093683A1
Electricity

3D HETEROGENEOUS INTEGRATED CRYSTALLINE PIEZOELECTRIC BULK ACOUSTIC RESONATORS

#7 | 2021-06-24
US20210194459A1
Electricity

BROADBAND ACOUSTIC WAVE RESONATOR (AWR) FILTERS

#8 | 2021-05-27
US20210159228A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#9 | 2020-10-01
US20200312854A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#10 | 2020-07-02
US20200212211A1
Electricity

Group III-nitride devices with improved RF performance and their methods of fabrication

#11 | 2020-05-07
US20200144369A1
Electricity

Integrated circuit components with substrate cavities

#12 | 2019-12-19
US20190386007A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#13 | 2019-01-31
US20190035790A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#14 | 2018-08-09
US20180226407A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#15 | 2017-07-20
US20170207222A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#16 | 2017-03-02
US20170062434A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#17 | 2016-11-03
US20160322360A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#18 | 2016-06-02
US20160155742A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#19 | 2016-03-31
US20160091776A1
Physics

Integrated Terahertz sensor

#20 | 2015-06-25
US20150179650A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#21 | 2014-06-26
US20140177995A1
Physics

Optical photonic circuit coupling

#22 | 2014-03-27
US20140086527A1
Physics

VERTICAL LIGHT COUPLER

#23 | 2014-01-16
US20140015021A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#24 | 2014-01-02
US20140003765A1
Physics

Waveguide integration on laser for alignment-tolerant assembly

#25 | 2013-10-24
US20130279845A1
Physics

Fabrication of planar light-wave circuits (PLCS) for optical I/O

#26 | 2012-10-25
US20120267721A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#27 | 2010-06-24
US20100155880A1
Electricity

Back gate doping for SOI substrates

#28 | 2010-03-25
US20100072533A1
Electricity

Asymmetric channel doping for improved memory operation for floating body cell (FBC) memory

#29 | 2009-10-29
US20090267153A1
Electricity

Localized spacer for a multi-gate transistor

#30 | 2009-07-02
US20090170279A1
Electricity

Method of preparing active silicon regions for CMOS or other devices

#31 | 2009-06-11
US20090146208A1
Electricity

Independently controlled, double gate nanowire memory cell with self-aligned contacts

#32 | 2009-01-15
US20090017589A1
Electricity

Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate

#33 | 2008-10-02
US20080237710A1
Electricity

Localized spacer for a multi-gate transistor

#34 | 2008-06-26
US20080149984A1
Electricity

Floating body memory cell having gates favoring different conductivity type regions

#35 | 2008-02-07
US20080029827A1
Electricity

Double gate transistor, method of manufacturing same, and system containing same

#36 | 2007-12-27
US20070296048A1
Electricity

Double gate transistor, method of manufacturing same, and system containing same

#37 | 2007-12-06
US20070278572A1
Electricity

Asymmetric channel doping for improved memory operation for floating body cell (FBC) memory

#38 | 2007-09-27
US20070224815A1
Electricity

Substrate patterning for multi-gate transistors

#39 | 2007-06-28
US20070148857A1
Electricity

Independently controlled, double gate nanowire memory cell with self-aligned contacts

#40 | 2007-06-14
US20070131983A1
Electricity

Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate

#41 | 2006-02-09
US20060030109A1
Electricity

Method to produce highly doped polysilicon thin films

#42 | 2005-11-17
US20050253192A1
Electricity

Stepped tip junction with spacer layer

InventorID:

496019 ⎘