Fredrick Fishburn

GROWTH OF GATE OXIDE LAYER WITH SILICON NITRIDE AND CONVERSION

STAGGERED BIT LINES FOR ADVANCED DRAM

INTEGRATED ENCAPSULATION DEPOSITION WITH METAL RECOVERY AND PASSIVATION

EPITAXIAL SILICON AND DOPED SILICON GERMANIUM SUPERLATTICE AND METHODS FOR PREPARING THE SAME

GROWTH OF THIN OXIDE LAYER IN VERTICAL CHANNEL STRUCTURE

BITLINE SURFACE TREATMENT AND ENCAPSULATION IN DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICES

SELF-ALIGNED BIT LINE FOR 4F2 DRAM

PRECURSOR STRUCTURE FOR SELF-ALIGNED BIT LINE AND STORAGE NODE CONTACTS FOR 4F2 DRAM

SELF-ALIGNED STORAGE NODE CONTACTS FOR 4F2 DRAM

DUAL WORK FUNCTION WORD LINE FOR 4F2

GATE ALL AROUND 4F2 DRAM

GROWTH OF THIN OXIDE LAYER WITH SILICON NITRIDE AND CONVERSION

STORAGE NODE CONTACT (SNC) JUNCTION FORMATION FOR THREE-DIMENSIONAL DYNAMIC RANDOM ACCESS MEMORY (DRAM)

DUAL FIELD EFFECT TRANSISTOR 4F2 CELL

HIGH ASPECT RATIO JUNCTION FORMATION THROUGH GAS PHASE DOPING

4F2 VERTICAL ACCESS TRANSISTOR WITH REDUCED FLOATING BODY EFFECT

METHOD OF MAKING SILICIDE IN HIGH-ASPECT RATIO STRUCTURES BY HYBRID PROCESSES

HOLE-TYPE SADP FOR 2D DRAM CAPACITOR

CARBON MOLD FOR DRAM CAPACITOR

SELF-ALIGNED VERTICAL BITLINE FOR THREE-DIMENSIONAL (3D) DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICES

SUPPORT LAYER FOR SMALL PITCH FILL

LINER TO FORM COMPOSITE HIGH-K DIELECTRIC

NH RADICAL THERMAL NITRIDATION TO FORM METAL SILICON NITRIDE FILMS

Three-dimensional dynamic random access memory (DRAM) and methods of forming the same

SEMICONDUCTOR ISOLATION BRIDGE FOR THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY

Method to scale dram with self aligned bit line process

System and methods for dram contact formation

Selection gate separation for 3D NAND

Replacement channel process for three-dimensional dynamic random access memory

3D pitch multiplication