Inventor profile of:

Mohan Vamsi Dunga

City:

Santa Clara, California

Country:

United States

Published Applications:

17

Last publication date:

2026-03-26

Top Assignees for applications by Mohan Vamsi Dunga

The entities that hold a legal rights for patent applications filed by inventor Dunga Mohan Vamsi:

Recent patent applications by Dunga Mohan Vamsi

Mohan Vamsi Dunga from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-03-26
US20260088092A1
Physics

PRE-CHARGE UNSELECTED BLOCK WORD LINE BEFORE PROGRAM

#2 | 2026-03-19
US20260082703A1
Electricity

CHARGE PUMP CIRCUIT CONFIGURATION IN NONVOLATILE MEMORY

#3 | 2026-01-01
US20260004822A1
Physics

REDUCTION IN CHIP AREA THROUGH DESIGN-TECHNOLOGY CO-OPTIMIZATION

#4 | 2025-10-23
US20250329393A1
Physics

NONVOLATILE MEMORY READ WITH SELECTIVE KICK VOLTAGE

#5 | 2025-06-26
US20250210108A1
Physics

WORD LINE SWITCH GATE VOLTAGE AND WELL VOLTAGE SEPARATION

#6 | 2025-01-02
US20250006244A1
Physics

ASYMMETRIC PASS VOLTAGE SCHEME FOR NON-VOLATILE MEMORY APPARATUS SIZE REDUCTION

#7 | 2024-11-21
US20240386930A1
Physics

WORD LINE DEPENDENT WORD LINE SWITCH DESIGN AND PROGRAMMING TECHNIQUES

#8 | 2020-05-14
US20200152281A1
Physics

Post write erase conditioning

#9 | 2019-12-19
US20190385680A1
Physics

Single pulse SLC programming scheme

#10 | 2019-06-13
US20190180823A1
Physics

Non-volatile memory and method for power efficient read or verify using lockout control

#11 | 2019-05-23
US20190156902A1
Physics

Post write erase conditioning

#12 | 2018-10-04
US20180286487A1
Physics

Post write erase conditioning

#13 | 2018-07-05
US20180189135A1
Physics

Memory write verification using temperature compensation

#14 | 2016-04-07
US20160099066A1
Physics

Bit line pre-charge with current reduction

#15 | 2014-01-02
US20140003150A1
Physics

System to reduce stress on word line select transistor during erase operation

#16 | 2013-11-14
US20130301358A1
Physics

Bit line BL isolation scheme during erase operation for non-volatile storage

#17 | 2010-07-08
US20100172187A1
Physics

Robust sensing circuit and method

InventorID:

527169 ⎘