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Inventor profile of:

Sridhar Samudrala

City:

Austin, Texas

Country:

United States

Published Applications:

21

Last publication date:

2024-12-26

Top Assignees for applications by Sridhar Samudrala

The entities that hold a legal rights for patent applications filed by inventor Samudrala Sridhar:

INTEL CORPORATION 15 Santa Clara, CA United States

Recent patent applications by Samudrala Sridhar

Sridhar Samudrala from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-12-26

US20240427600A1

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

#2 | 2024-02-22

US20240061683A1

Vector friendly instruction format and execution thereof

#3 | 2022-04-28

US20220129274A1

Vector friendly instruction format and execution thereof

#4 | 2020-12-17

US20200394042A1

Vector friendly instruction format and execution thereof

#5 | 2019-07-25

US20190227800A1

Vector friendly instruction format and execution thereof

#6 | 2019-04-11

US20190108030A1

SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK

#7 | 2019-04-11

US20190108029A1

SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK

#8 | 2017-02-09

US20170039033A1

Double rounded combined floating-point multiply and add

#9 | 2016-03-17

US20160077802A1

Double rounded combined floating-point multiply and add

#10 | 2015-01-22

US20150026671A1

Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs

#11 | 2014-12-18

US20140372727A1

Instruction and logic to provide vector blend and permute functionality

#12 | 2014-09-18

US20140281419A1

Combined floating point multiplier adder with intermediate rounding logic

#13 | 2014-05-29

US20140149724A1

Vector friendly instruction format and execution thereof

#14 | 2014-01-02

US20140006467A1

Double rounded combined floating-point multiply and add

#15 | 2013-12-05

US20130326199A1

METHOD AND APPARATUS FOR CONTROLLING A MXCSR

#16 | 2013-11-14

US20130305020A1

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

#17 | 2012-10-04

US20120254592A1

SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INTO A DESTINATION REGISTER AND COMPRESSING A SOURCE REGISTER INTO A DESTINATION MEMORY LOCATION

#18 | 2012-10-04

US20120254588A1

SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK

#19 | 2012-03-29

US20120079253A1

Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation

#20 | 2012-03-29

US20120079233A1

Vector logical reduction operation implemented using swizzling on a semiconductor chip

#21 | 2012-03-29

US20120078992A1

Functional unit for vector integer multiply add instruction

InventorID:

532519 ⎘