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Inventor profile of:

Dal-Hee LEE

City:

Seoul

Country:

South Korea

Published Applications:

21

Last publication date:

2024-06-20

Top Assignees for applications by Dal-Hee LEE

The entities that hold a legal rights for patent applications filed by inventor LEE Dal-Hee:

SAMSUNG ELECTRONICS CO., LTD. 10 Suwon-si, South Korea
SAMSUNG ELECTRONICS CO. LTD. 6 Suwon-si, Gyeonggi-do, South Korea
SAMSUNG ELECTRONICS CO., LTD. 5 Gyeonggi-Do, South Korea
Samsung Electronics Co., Ltd 3 , South Korea

Recent patent applications by LEE Dal-Hee

Dal-Hee LEE from Seoul, KR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-06-20

US20240203974A1

INTEGRATED CIRCUITS HAVING CROSS-COUPLE CONSTRUCTS AND SEMICONDUCTOR DEVICES INCLUDING INTEGRATED CIRCUITS

#2 | 2022-10-27

US20220345118A1

Latch circuit, flip-flop circuit including the same

#3 | 2022-05-12

US20220149032A1

Integrated circuits having cross-couple constructs and semiconductor devices including integrated circuits

#4 | 2021-10-21

US20210328582A1

Latch circuit, flip-flop circuit including the same

#5 | 2020-07-23

US20200235126A1

Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped for mitigating electromigration

#6 | 2020-04-23

US20200126968A1

Standard cell for removing routing interference between adjacent pins and device including the same

#7 | 2020-02-13

US20200051977A1

Integrated circuit including multiple-height cell and method of manufacturing the integrated circuit

#8 | 2019-12-19

US20190383875A1

Scan flip-flop and scan test circuit including the same

#9 | 2019-06-27

US20190198491A1

Integrated circuits having cross-couple constructs and semiconductor devices including integrated circuits

#10 | 2018-10-11

US20180294280A1

Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration

#11 | 2017-11-16

US20170328954A1

Scan flip-flop and scan test circuit including the same

#12 | 2017-10-12

US20170294430A1

Standard cell for removing routing interference between adjacent pins and device including the same

#13 | 2017-04-27

US20170116366A1

Engineering change order (ECO) cell, layout thereof and integrated circuit including the ECO cell

#14 | 2017-03-30

US20170093401A1

Integrated circuit and semiconductor device including the same

#15 | 2017-01-12

US20170011160A1

Methods of generating integrated circuit layout using standard cell library

#16 | 2016-09-29

US20160285452A1

Integrated circuit and semiconductor device including the same

#17 | 2016-04-07

US20160097811A1

Scan flip-flop and scan test circuit including the same

#18 | 2016-02-25

US20160055285A1

Methods of generating integrated circuit layout using standard cell library

#19 | 2016-02-04

US20160034627A1

Method and program for designing integrated circuit

#20 | 2015-08-27

US20150244366A1

Integrated circuit and semiconductor device including the same

#21 | 2013-12-05

US20130320405A1

Semiconductor device having decoupling capacitors and dummy transistors

InventorID:

553947 ⎘