Mark L. Doczy

Perpendicular STTM multi-layer insert free layer

Method for fabricating transistor with thinned channel

Perpendicular spin transfer torque memory (PSTTM) devices with enhanced perpendicular anisotropy and methods to form same

Method for fabricating transistor with thinned channel

Perpendicular spin transfer torque memory (pSTTM) devices with enhanced stability and method to form same

High stability free layer for perpendicular spin torque transfer memory

Perpendicular STTM free layer including protective cap

LAYER TRANSFERRED FERROELECTRIC MEMORY DEVICES

Ferromagnetic resonance testing of buried magnetic layers of whole wafer

Texture breaking layer to decouple bottom electrode from PMTJ device

Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs) and the resulting structures

Interconnect capping process for integration of MRAM devices and the resulting structures

Electrical contacts for magnetoresistive random access memory devices

Unipolar current switching in perpendicular magnetic tunnel junction (pMTJ) devices through reduced bipolar coercivity

Memory cells with enhanced tunneling magnetoresistance ratio, memory devices and systems including the same

Spin transfer torque memory (STTM), methods of forming the same using a non-conformal insulator, and devices including the same

Method for fabricating transistor with thinned channel

Extreme high mobility CMOS logic

Techniques for forming spin-transfer torque memory having a dot-contacted free magnetic layer

Techniques for forming spin-transfer torque memory (STTM) elements having annular contacts

Method for fabricating transistor with thinned channel

Extreme high mobility CMOS logic

Decreased switching current in spin-transfer torque memory

Extreme high mobility CMOS logic

Decreased switching current in spin-transfer torque memory

Extreme high mobility CMOS logic

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Extreme high mobility CMOS logic

Gate electrode having a capping layer

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Inducing strain in the channels of metal gate transistors

Method for fabricating transistor with thinned channel

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Forming integrated circuits with replacement metal gate electrodes

Forming abrupt source drain metal gate transistors

Field effect transistor with metal source/drain regions

CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

METAL GATE DEVICE WITH REDUCED OXIDATION OF A HIGH-K GATE DIELECTRIC

Reducing Ambipolar Conduction in Carbon Nanotube Transistors

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Gate electrode having a capping layer

Dielectric interface for group III-V semiconductor device

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Semiconductor device with a high-k gate dielectric and a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric

Block contact architectures for nanoscale channel transistors

Reducing oxidation under a high K gate dielectric

Lateral undercut of metal gate in SOI device

Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode

CMOS device with metal and silicide gate electrodes and a method for making it

Sb-based CMOS devices

Forming high-k dielectric layers on smooth substrates

Highly-selective metal etchants

Pinning layer for low resistivity N-type source drain ohmic contacts

Gate dielectric materials for group III-V enhancement mode transistors

In situ processing for ultra-thin gate oxide scaling

Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors

Transistor including flatband voltage control through interface dipole engineering

Gate electrode having a capping layer

Device with scavenging spacer layer

Quantum dot nonvolatile transistor

Extreme high mobility CMOS logic

Dielectric interface for group III-V semiconductor device

Method of fabricating CMOS devices having a single work function gate electrode by band gap engineering and article made thereby

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Reducing gate dielectric material to form a metal gate electrode extension

Lateral undercut of metal gate in SOI device

Planarizing a semiconductor structure to form replacement metal gates

Reducing the dielectric constant of a portion of a gate dielectric

Block contact architectures for nanoscale channel transistors

Strained field effect transistors

Method for fabricating transistor with thinned channel

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Metal gate device with reduced oxidation of a high-k gate dielectric

Semiconductor device with a high-k gate dielectric and a metal gate electrode

Compensating for induced strain in the channels of metal gate transistors

Semiconductor device with a high-k gate dielectric and a metal gate electrode

Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit

Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

Field effect transistor with metal source/drain regions

Method for making a semiconductor device having a high-k gate dielectric

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric

Inhibiting growth under high dielectric constant films

Forming field effect transistors from conductors

Quantum well transistor using high dielectric constant dielectric layer

Tailoring channel dopant profiles

Method for making a semiconductor device having a high-k gate dielectric

Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode

Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode

Method for making a semiconductor device having a high-K gate dielectric and a titanium carbide gate electrode

Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode

Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode

Semiconductor channel on insulator structure

Method for making a semiconductor device having a high-k gate dielectric