Inventor profile of:

Yi Yang

City:

Gilbert, Arizona

Country:

United States

Published Applications:

25

Last publication date:

2025-08-14

Top Assignees for applications by Yi Yang

The entities that hold a legal rights for patent applications filed by inventor Yang Yi:

Recent patent applications by Yang Yi

Yi Yang from Gilbert, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-08-14
US20250259055A1
Physics

NEURAL NETWORK WITH POINT GRID CONVOLUTIONAL LAYER

#2 | 2024-07-04
US20240219632A1
Physics

TECHNOLOGIES FOR INTEGRATED GRADED INDEX LENSES IN PHOTONIC CIRCUITS

#3 | 2024-06-27
US20240213131A1
Electricity

DIRECT PLATING OF COPPER ON DIELECTRICS FOR GLASS CORE PLATING

#4 | 2024-06-06
US20240186264A1
Electricity

POLYMER LAYERS FOR ADHESIVE PROMOTION AND STRESS MANAGEMENT IN GLASS LAYERS IN INTEGRATED CIRCUIT DEVICES

#5 | 2024-04-04
US20240113048A1
Electricity

INTEGRATED HORIZONTAL VARISTOR ON GLASS CORE FOR VOLTAGE REGULATION

#6 | 2024-04-04
US20240113046A1
Electricity

EMBEDDED THIN FILM VARISTOR IN THROUGH GLASS VIAS

#7 | 2024-04-04
US20240111089A1
Physics

NANOROD COATING BETWEEN TWO OPTICAL MEDIUMS

#8 | 2024-01-04
US20240006300A1
Electricity

SUBSTRATES HAVING ADHESION PROMOTOR LAYERS AND RELATED METHODS

#9 | 2024-01-04
US20240006299A1
Electricity

SINX BASED SURFACE FINISH ARCHITECTURE

#10 | 2024-01-04
US20240006298A1
Electricity

SUBSTRATE HAVING ONE OR MORE ELECTRICAL INTERCONNECTS

#11 | 2024-01-04
US20240006297A1
Electricity

SILICIDE AND SILICON NITRIDE LAYERS BETWEEN A DIELECTRIC AND COPPER

#12 | 2024-01-04
US20240006291A1
Electricity

POCKETED COPPER IN FIRST LAYER INTERCONNECT AND METHOD

#13 | 2024-01-04
US20240006285A1
Electricity

SUBSTRATES HAVING ADHESION PROMOTOR LAYERS AND RELATED METHODS

#14 | 2024-01-04
US20240006283A1
Electricity

EDGE DELAMINATION AND CRACK PREVENTION METHODS FOR SINX AND TI-CU ENABLED PACKAGES

#15 | 2023-12-28
US20230420389A1
Electricity

STRESS-REDUCING DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES

#16 | 2023-12-28
US20230420353A1
Electricity

ASYMMETRICAL DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES

#17 | 2023-12-28
US20230420346A1
Electricity

SINGLE LITHOGRAPHY METHODS FOR INTERCONNECT ARCHITECTURES

#18 | 2023-12-28
US20230420322A1
Electricity

ORGANIC ADHESION PROMOTOR FOR DIELECTRIC ADHESION TO A COPPER TRACE

#19 | 2023-12-14
US20230402368A1
Electricity

TECHNOLOGIES FOR THIN FILM RESISTORS IN VIAS

#20 | 2023-12-07
US20230395467A1
Electricity

GLASS CORE ARCHITECTURES WITH DIELECTRIC BUFFER LAYER BETWEEN GLASS CORE AND METAL VIAS AND PADS

#21 | 2023-12-07
US20230395445A1
Electricity

GLASS CORE ARCHITECTURES WITH DIELECTRIC BUFFER LAYER BETWEEN GLASS CORE AND METAL VIAS AND PADS

#22 | 2023-10-05
US20230317614A1
Electricity

SURFACE FUNCTIONALIZATION OF SINX THIN FILM BY WET ETCHING FOR IMPROVED ADHESION OF METAL-DIELECTRIC FOR HSIO

#23 | 2023-10-05
US20230317584A1
Electricity

PLASMA-INDUCED SURFACE FUNCTIONALIZATION OF SINX THIN FILM FOR IMPROVED ADHESION OF METAL-DIELECTRIC FOR HSIO

#24 | 2023-10-05
US20230317583A1
Electricity

MODIFICATION OF SINX THIN FILM FOR IMPROVED ADHESION OF METAL-DIELECTRICS FOR HSIO PACKAGING

#25 | 2023-03-23
US20230085997A1
Electricity

METHODS AND APPARATUS TO IMPROVE ADHESION BETWEEN METALS AND DIELECTRICS IN CIRCUIT DEVICES

InventorID:

5689345 ⎘