Boise, Idaho
United States
42
2026-03-05
The entities that hold a legal rights for patent applications filed by inventor Puzzilli Giuseppina:
Giuseppina Puzzilli from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MITIGATING SLOW READ DISTURB IN A MEMORY SUB-SYSTEM
#2 | 2024-06-06MITIGATING SLOW READ DISTURB IN A MEMORY SUB-SYSTEM
#3 | 2024-04-25SIMULTANEOUS STATISTICAL MULTI-SUBBLOCK VERIFY FOR NAND MEMORIES
#4 | 2024-04-18DECK RESET READ
#5 | 2023-02-09Partitioned memory having error detection capability
#6 | 2022-12-08Adjusting a preprogram voltage based on use of a memory device
#7 | 2022-11-10Implementing fault tolerant page stripes on low density memory systems
#8 | 2022-11-03Read calibration based on ranges of program/erase cycles
#9 | 2022-11-03Separate partition for buffer and snapshot memory
#10 | 2022-10-27Storing highly read data at low impact read disturb pages of a memory device
#11 | 2022-10-20Mitigating slow read disturb in a memory sub-system
#12 | 2022-09-29Latent read disturb mitigation in memory devices
#13 | 2022-09-15Temperature-dependent operations in a memory device
#14 | 2022-09-15Partitions within snapshot memory for buffer and snapshot memory
#15 | 2022-07-07Read voltage calibration for copyback operation
#16 | 2022-06-23Setting an initial erase voltage using feedback from previous operations
#17 | 2022-06-23Threshold voltage distribution adjustment for buffer
#18 | 2022-06-23Adjusting a preprogram voltage based on use of a memory device
#19 | 2022-06-16Trims corresponding to program/erase cycles
#20 | 2022-03-03Read voltage calibration for copyback operation
#21 | 2022-03-03Read window based on program/erase cycles
#22 | 2022-03-03Determining a read voltage based on a change in a read window
#23 | 2022-03-03Separate trims for buffer and snapshot
#24 | 2022-03-03Read calibration based on ranges of program/erase cycles
#25 | 2022-03-03Data management during a copyback operation
#26 | 2022-02-24TRIM DETERMINATION BASED ON POWER AVAILABILITY
#27 | 2022-02-17Threshold voltage based on program/erase cycles
#28 | 2022-02-17Threshold voltage distribution adjustment for buffer
#29 | 2022-02-17Partitioned memory having error detection capability
#30 | 2022-02-17Partitions within snapshot memory for buffer and snapshot memory
#31 | 2022-02-17Separate partition for buffer and snapshot memory
#32 | 2022-02-17Trims corresponding to logical unit quantity
#33 | 2021-11-30Read window based on program/erase cycles
#34 | 2021-07-01Implementing fault tolerant page stripes on low density memory systems
#35 | 2019-04-04Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND
#36 | 2015-01-29METHODS OF PROGRAMMING MEMORY DEVICES
#37 | 2014-04-24Methods of programming memory devices
#38 | 2013-12-12In-field block retiring
#39 | 2012-12-27In-field block retiring
#40 | 2011-08-18Memory array having memory cells coupled between a programmable drain select gate and a non-programmable source select gate
#41 | 2011-06-23Erase operations and apparatus for a memory device
#42 | 2011-03-10Data line management in a memory device
570699 ⎘