Vivek De

System, apparatus and method for sensor-driven and heuristic-based minimum energy point tracking in a processor

Apparatus and method for approximate trilinear interpolation for scene reconstruction

Apparatus and method for approximate trilinear interpolation for scene reconstruction

Non-linear clamp strength tuning method and apparatus

Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency

Controlling a processing performance level depending on energy expenditure

System, apparatus and method for sensor-driven and heuristic-based minimum energy point tracking in a processor

Multiple output voltage conversion

Device, system, and method to change a consistency of behavior by a cell circuit

Minimum delay error detection and correction for pulsed latches

Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency

Physically unclonable function implemented with spin orbit coupling based magnetic memory

Voltage regulator efficiency-aware global-minimum energy tracking

Master-slave controller architecture

Peak-delivered-power circuit for a voltage regulator

Disabling cache portions during low voltage operations

Spin transfer torque based memory elements for programmable device arrays

Disabling cache portions during low voltage operations

Spin transfer torque based memory elements for programmable device arrays

Memory cell supply voltage control based on error detection

DC-DC converter switching transistor current measurement technique

Disabling cache portions during low voltage operations

Circuits and methods for reducing minimum supply for register file cells

Logic circuits using carbon nanotube transistors

Memory cell supply voltage control based on error detection

Capacitor, method of increasing a capacitance area of same, and system containing same

Methods of forming carbon nanotube transistors for high speed circuit operation and structures formed thereby

Increasing the surface area of a memory cell capacitor

Circuits and methods for reducing minimum supply for register file cells

Disabling cache portions during low voltage operations

Sequential circuit with error detection

Multiphase transformer for a multiphase DC-DC converter

Reducing minimum operating voltage through hybrid cache design

Carbon nanotube fuse element

Increasing the surface area of a memory cell capacitor

Capacitor, method of increasing a capacitance area of same, and system containing same

Memory cell bit valve loss detection and restoration

Address hashing to help distribute accesses across portions of destructive read cache memory

Memory having bit line with resistor(s) between memory cells

Logic circuits using carbon nanotube transistors

Sleep transistor array apparatus and method with leakage control circuitry

Memory cell supply voltage control based on error detection

Error-detection flip-flop

Level shifter

Multi-ported register files

Multiphase transformer for a multiphase DC-DC converter

DC-DC converter switching transistor current measurement technique

Voltage regulation using digital voltage control

Low-voltage, buffered bandgap reference with selectable output voltage

CPU power delivery system

DC/DC converters using dynamically-adjusted variable-size switches

Stepwise drivers for DC/DC converters

Floating-body DRAM using write word line for increased retention time

Timing circuit for separate positive and negative edge placement in a switching DC-DC converter

Floating-body DRAM using write word line for increased retention time