Arvind Kumar

Heterogeneous integrated multi-chip cooler module

HETEROGENEOUS INTEGRATION STRUCTURE WITH VOLTAGE REGULATION

CLUSTERING FINE PITCH MICRO-BUMPS FOR PACKAGING AND TEST

STACKED 3D CACHE CONFIGURATION WITH ON-CHIP POWER SUPPORT

ACTIVE BRIDGE FOR CHIPLET AND MODULE INTER-COMMUNICATION

Multichannel memory to augment local memory

ARCHITECTURE AND DEVICE USING OPTICAL ELEMENT AND COMPUTER CHIP FOR OPTICAL SIGNAL TRANSMISSION

ELECTRICAL-OPTICAL BRIDGE CHIP AND INTEGRATED CIRCUIT PACKAGING STRUCTURE

Interconnection structures for high bandwidth data transfer

Memory and logic chip stack with a translator chip

NVM-BASED HIGH-CAPACITY NEURAL NETWORK INFERENCE ENGINE

Trusted field programmable gate array

Tamper-resistant circuit, back-end of the line memory and physical unclonable function for supply chain protection

Tamper resistant obfuscation circuit

Precision thin electronics handling integration

Optimal placement of data structures in a hybrid memory based inference computing platform

Secure chip identification using resistive processing unit as a physically unclonable function

Back-side memory element with local memory select transistor

Optimized hierarchical scratchpads for enhanced artificial intelligence accelerator core utilization

Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network

Heterogeneous integration structure for artificial intelligence computing

FinFET resistive switching device having interstitial charged particles for memory and computational applications

Through-silicon-via fabrication in planar quantum devices

Generating key material for information security using a resistive processing unit (RPU) accelerator array as a physically unclonable function (PUF)

Lithium drifted thin film transistors for neuromorphic computing

Ternary content addressable memory

Direct bonded heterogeneous integration packaging structures

INTEGRATED CIRCUIT (IC) PACKAGE WITH HETROGENOUS IC CHIP INTERPOSER

Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration

Virtualization in hierarchical cortical emulation frameworks

SELF-ORIENTATION AND SELF-PLACEMENT OF COMPUTING DEVICES IN A FLUID

Direct bonded heterogeneous integration packaging structures

Back-side memory element with local memory select transistor

Ternary content addressable memory

Wafer-scale power delivery

Lithium-drift based resistive processing unit for accelerating machine learning training

Back-side memory element with local memory select transistor

Wafer-scale power delivery

FinFET vertical flash memory

Heterogeneous integration using wafer-to-wafer stacking with die size adjustment

Heterogeneous integration using wafer-to-wafer stacking with die size adjustment

Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration

Visual object and event detection and prediction system using saccades

FINFET DEVICE WITH LOW RESISTANCE FINS

High memory bandwidth neuromorphic computing system

Three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes

Heterogeneous integration using wafer-to-wafer stacking with die size adjustment

Visual object and event detection and prediction system using saccades

Cooling and power delivery for a wafer level computing board

Space-efficient dynamic addressing in very large sparse networks

Ternary content addressable memory

Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration

Finfet crosspoint flash memory

Asymmetric high-k dielectric for reducing gate induced drain leakage

FinFET vertical flash memory

Channel region dopant control in fin field effect transistor

Trapping dislocations in high-mobility fins below isolation layer

Replacement gate structure for enhancing conductivity

Replacement gate structure for enhancing conductivity

Structure and method for effective device width adjustment in finFET devices using gate workfunction shift

Method of forming channel region dopant control in fin field effect transistor

Junction butting in SOI transistor with embedded source/drain

Shallow trench isolation structures

MEMORY DEVICE EMPLOYING AN INVERTED U-SHAPED FLOATING GATE

Finfet crosspoint flash memory

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Intrinsic Channel Planar Field Effect Transistors Having Multiple Threshold Voltages

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Shallow trench isolation structures

Shallow trench isolation structures

Shallow trench isolation structures

Techniques for enabling multiple Vdevices using high-K metal gate stacks

Techniques for enabling multiple Vdevices using high-K metal gate stacks

Techniques for enabling multiple Vdevices using high-K metal gate stacks

Substrate solution for back gate controlled SRAM with coexisting logic devices

Substrate solution for back gate controlled SRAM with coexisting logic devices