🔗 Permalink

Inventor profile of:

Bok Eng Cheah

City:

Bayan Lepas

Country:

Malaysia

Published Applications:

30

Last publication date:

2020-10-15

Top Assignees for applications by Bok Eng Cheah

The entities that hold a legal rights for patent applications filed by inventor Cheah Bok Eng:

INTEL CORPORATION 26 Santa Clara, CA United States

Recent patent applications by Cheah Bok Eng

Bok Eng Cheah from Bayan Lepas, MY has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-10-15

US20200325711A1

Fixed constructions

Micro-hinge for an electronic device

#2 | 2019-07-11

US20190215953A1

Mutual inductance suppressor for crosstalk immunity enhancement

#3 | 2019-07-04

US20190208620A1

3D high-inductive ground plane for crosstalk reduction

#4 | 2019-03-28

US20190093402A1

Fixed constructions

Micro-hinge for an electronic device

#5 | 2018-12-20

US20180366407A1

Over-molded IC packages with embedded voltage reference plane and heater spreader

#6 | 2018-10-11

US20180294252A1

Stacked package assembly with voltage reference plane

#7 | 2018-05-24

US20180145014A1

HIGH DENSITY SECOND LEVEL INTERCONNECTION FOR BUMPLESS BUILD UP LAYER (BBUL) PACKAGING TECHNOLOGY

#8 | 2017-11-30

US20170345763A1

Flexible packaging architecture

#9 | 2017-06-22

US20170181289A1

Flexible integrated circuit that includes an antenna

#10 | 2017-06-15

US20170170799A1

Capacitive compensation structures using partially meshed ground planes

#11 | 2017-06-15

US20170170676A1

Foldable fabric-based packaging solution

#12 | 2017-03-30

US20170093064A1

Board-edge interconnection module with integrated capacitive coupling for enabling ultra-mobile computing devices

#13 | 2017-01-19

US20170018530A1

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

#14 | 2017-01-12

US20170012020A1

Embedded die-down package-on-package device

#15 | 2016-12-29

US20160380386A1

ELECTROSTATIC DISCHARGE FOR ELECTRONIC DEVICE COUPLING

#16 | 2016-11-24

US20160343686A1

Integrated circuit packaging techniques and configurations for small form-factor or wearable devices

#17 | 2016-11-10

US20160327977A1

Flexible system-in-package solutions for wearable devices

#18 | 2016-05-26

US20160148866A1

Electrical interconnect for an electronic package

#19 | 2016-05-12

US20160132077A1

Micro-hinge for an electronic device

#20 | 2016-05-12

US20160130849A1

Fixed constructions

Micro-hinge for an electronic device

#21 | 2016-01-07

US20160005718A1

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

#22 | 2015-10-01

US20150277506A1

MICRO-HINGE FOR AN ELECTRONIC DEVICE

#23 | 2015-10-01

US20150277505A1

Low-profile hinge for an electronic device

#24 | 2015-07-16

US20150201497A1

HIGH-DENSITY INTER-PACKAGE CONNECTIONS FOR ULTRA-THIN PACKAGE-ON-PACKAGE STRUCTURES, AND PROCESSES OF FORMING SAME

#25 | 2014-10-02

US20140291866A1

Embedded die-down package-on-package device

#26 | 2014-04-03

US20140091442A1

High density second level interconnection for bumpless build up layer (BBUL) packaging technology

#27 | 2013-12-26

US20130341803A1

Method to enable controlled side chip interconnection for 3D integrated packaging system

#28 | 2012-12-20

US20120319293A1

MICROELECTRONIC DEVICE, STACKED DIE PACKAGE AND COMPUTING SYSTEM CONTAINING SAME, METHOD OF MANUFACTURING A MULTI-CHANNEL COMMUNICATION PATHWAY IN SAME, AND METHOD OF ENABLING ELECTRICAL COMMUNICATION BETWEEN COMPONENTS OF A STACKED-DIE PACKAGE

#29 | 2011-06-16

US20110140268A1

High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same

#30 | 2008-12-25

US20080315388A1

VERTICAL CONTROLLED SIDE CHIP CONNECTION FOR 3D PROCESSOR PACKAGE

InventorID:

583235 ⎘