Feras Eid

MICROELECTRONIC DEVICES DESIGNED WITH MOLD PATTERNING TO CREATE PACKAGE-LEVEL COMPONENTS FOR HIGH FREQUENCY COMMUNICATION SYSTEMS

INTEGRATED CIRCUIT PACKAGES HAVING TOPSIDE POWER DELIVERY IN 3 DIMENSIONAL DIE STACKS

HYBRID-BONDED IC DIE HAVING TOPOGRAPHIC SURFACE FEATURES

EXTENDED HYBRID BONDING WITH A PHOTONIC INTERFACE

MULTI-LAYER INTEGRATED RING RESONATORS AND WAVEGUIDE INTERCONNECT STACKS

PHOTONIC STACKS FOR MULTI-TIER PHOTONIC INTEGRATED CIRCUIT PACKAGE ASSEMBLIES

INTEGRATED CIRCUIT PACKAGES INCLUDING 3 DIMENSIONAL DIE STACKS WITH A DIE HAVING A SIDEWALL MODIFICATION

INTEGRATED CIRCUIT PACKAGES INCLUDING A STRUCTURAL DIE COUPLED TO A HIGH THERMAL CONDUCTIVITY MATERIAL IN 3 DIMENSIONAL DIE STACKS

INTEGRATED CIRCUIT PACKAGES INCLUDING A HIGH THERMAL CONDUCTIVITY MATERIAL COUPLED TO A SUBSTRATE WITH MICROCHANNELS IN 3 DIMENSIONAL DIE STACKS

INTEGRATED CIRCUIT PACKAGES INCLUDING A HEAT SPREADER HAVING A HIGH THERMAL CONDUCTIVITY MATERIAL IN 3 DIMENSIONAL DIE STACKS

INTEGRATED CIRCUIT PACKAGES INCLUDING A HIGH THERMAL CONDUCTIVITY MATERIAL IN 3 DIMENSIONAL DIE STACKS

DISAGGREGATION AND ASSEMBLY OF PHOTONICS INTEGRATED CIRCUITS USING PHOTONIC VIAS

OPTICAL COUPLING USING SHIFTED OUT-OF-PLANE LIGHT PROPAGATION

TECHNOLOGIES FOR LOW-CROSSTALK MULTILAYER WAVEGUIDE STACKS

INTEGRATION OF SELF-ASSEMBLY FEATURES WITH PHOTONIC CIRCUITS

MICROELECTRONIC ASSEMBLIES

INTEGRATED CIRCUIT PACKAGES INCLUDING MULTI-DIE STACKS HAVING TAPERED SIDEWALLS

THERMAL PERFORMANCE IN HYBRID BONDED 3D DIE STACKS

CONFIGURABLE CARRIER FOR TRANSFER AND SELF-ASSEMBLY OF MULTIPLE INTEGRATED CIRCUIT DEVICES

HANDLING ASSEMBLY, HANDLING SYSTEM AND METHOD

SELF-ASSEMBLY METHOD AND EQUIPMENT

SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS

FINE-GRAIN INTEGRATION OF GROUP III-V DEVICES

SELECTIVE LAYER TRANSFER WITH GLASS PANELS

HYBRID BONDING OF THIN DIE STRUCTURES BY SELF-ALIGNMENT ASSISTED ASSEMBLY

SELF-ALIGNMENT ASSISTED ASSEMBLY OF MULTI-LEVEL DIE COMPLEXES

SELECTIVE TRANSFER OF THERMAL MANAGEMENT DIES

IC ASSEMBLIES WITH SELF-ALIGNMENT STRUCTURES HAVING ZERO MISALIGNMENT

TILT MITIGATION IN SELF-ALIGNMENT ASSISTED ASSEMBLY OF IC DIE

SUPERHYDROPHOBIC SURFACES FOR LIQUID CONTAINMENT IN SELF-ALIGNMENT ASSISTED ASSEMBLY OF INTEGRATED CIRCUIT DIE STACKS

SELF-ALIGNMENT ASSISTED ASSEMBLY ON A STRUCTURAL WAFER FOR HYBRID BONDED DIE STACKS

PRE-ASSEMBLY WARPAGE COMPENSATION OF THIN DIE STRUCTURES

CONFORMAL COATINGS WITH SPATIALLY DEFINED SURFACE ENERGIES FOR DIE-TO-WAFER SELF-ALIGNMENT ASSISTED ASSEMBLY

IC ASSEMBLIES WITH METAL PASSIVATION AT BOND INTERFACES

STRUCTURAL SUPPORT LAYER TO PROTECT SELECTIVE TRANSFER LAYER DURING LASER EXPOSURE OF UNBONDED WAFERS

ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRANSFERS

REMOVAL OF DEFECTIVE DIES ON DONOR WAFERS FOR SELECTIVE LAYER TRANSFER

CROSS-LINKED HYDROPHOBIC COATING WITH PLASMA RESISTANCE FOR DIE-TO-WAFER SELF-ALIGNMENT ASSISTED ASSEMBLY

PROTECTIVE DEBONDING STACK FOR SELECTIVE TRANSFER

SELECTIVE TRANSFER OF OPTICAL AND OPTO-ELECTRONIC COMPONENTS

SELECTIVE LAYER TRANSFER

BLANKET WAFER LASER PRE-EXPOSURE FOR FAST SELECTIVE LAYER TRANSFERS

MAGNETIC INDUCTORS FOR SEMICONDUCTOR PACKAGING

MICROELECTRONIC ASSEMBLIES

METHODS AND APPARATUS FOR SELF-ALIGNING BATCH PICK AND PLACE DIE BONDING

ON DIE FLEXURE CONTROL DEVICE AND METHOD

MICROELECTRONIC ASSEMBLIES WITH INDUCTORS IN DIRECT BONDING REGIONS

POWER DELIVERY STRUCTURES

DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES

DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES

MICROELECTRONIC DEVICES DESIGNED WITH MOLD PATTERNING TO CREATE PACKAGE-LEVEL COMPONENTS FOR HIGH FREQUENCY COMMUNICATION SYSTEMS

HYBRID BACKSIDE THERMAL STRUCTURES FOR ENHANCED IC PACKAGES

IC DIE COMPOSITES WITH INORGANIC INTER-DIE FILL STRUCTURES

QUASI-MONOLITHIC DIE ARCHITECTURES

QUASI-MONOLITHIC DIE ARCHITECTURES

DEVICE, METHOD, AND SYSTEM TO PROTECT THROUGH-DIELECTRIC VIAS OF A COMPOSITE CHIPLET

DEVICE, METHOD, AND SYSTEM TO MITIGATE WARPAGE OF A COMPOSITE CHIPLET

DIE CRACK MITIGATION IN MULTI-CHIP COMPOSITE IC STRUCTURES

SPLIT METALLIZATION LAYERS IN MULTICHIP DEVICES

PACKAGE ARCHITECTURE FOR QUASI-MONOLITHIC CHIP WITH BACKSIDE POWER

THERMALLY ENHANCED STRUCTURAL MEMBER AND/OR BOND LAYER FOR MULTICHIP COMPOSITE DEVICES

THERMAL MANAGEMENT OF BASE DIES IN MULTICHIP COMPOSITE DEVICES

INTEGRATED CONFORMAL THERMAL HEAT SPREADER FOR MULTICHIP COMPOSITE DEVICES

INORGANIC MATERIAL DEPOSITION FOR INTER-DIE FILL IN MULTI-CHIP COMPOSITE STRUCTURES

TEMPLATE STRUCTURE FOR QUASI-MONOLITHIC DIE ARCHITECTURES

PHOTONIC QUASI-MONOLITHIC DIE ARCHITECTURES

Thermal management in integrated circuit packages

MICROELECTRONIC DEVICES DESIGNED WITH MOLD PATTERNING TO CREATE PACKAGE-LEVEL COMPONENTS FOR HIGH FREQUENCY COMMUNICATION SYSTEMS

BOND HEAD DESIGN FOR THERMAL COMPRESSION BONDING

NON-PLANAR PEDESTAL FOR THERMAL COMPRESSION BONDING

PACKAGE STRUCTURES WITH NON-UNIFORM INTERCONNECT FEATURES

PACKAGE STRUCTURES WITH COLLAPSE CONTROL FEATURES

CHASSIS CUSTOMIZATION WITH HIGH THROUGHPUT ADDITIVE MANUFACTURED MODIFICATION STRUCTURES

POROUS MESH STRUCTURES FOR THE THERMAL MANAGEMENT OF INTEGRATED CIRCUIT DEVICES

DIE BACKSIDE FILM WITH OVERHANG FOR DIE SIDEWALL PROTECTION

PACKAGE STRUCTURES WITH PATTERNED DIE BACKSIDE LAYER

DUAL FEED COLD SPRAY NOZZLE WITH SEPARATE TEMPERATURE AND FEEDING RATE CONTROL

METAL MATRIX COMPOSITE LAYERS HAVING GRADED FILLER CONTENT FOR HEAT DISSIPATION FROM INTEGRATED CIRCUIT DEVICES

METAL MATRIX COMPOSITE LAYERS FOR HEAT DISSIPATION FROM INTEGRATED CIRCUIT DEVICES

REUSABLE COMPOSITE STENCIL FOR SPRAY PROCESSES

ADDITIVELY MANUFACTURED HEAT DISSIPATION DEVICE

Microelectronic devices designed with mold patterning to create package-level components for high frequency communication systems

Thermal management solutions for embedded integrated circuit devices

Microelectronic assemblies

TECHNOLOGIES FOR HIGH THROUGHPUT ADDITIVE MANUFACTURING FOR INTEGRATED CIRCUIT COMPONENTS

CONFORMAL POWER DELIVERY STRUCTURES OF 3D STACKED DIE ASSEMBLIES

TECHNOLOGIES FOR HIGH THROUGHPUT ADDITIVE MANUFACTURING FOR INTEGRATED CIRCUIT COMPONENTS

TECHNOLOGIES FOR HIGH THROUGHPUT ADDITIVE MANUFACTURING FOR INTEGRATED CIRCUIT COMPONENTS

COOLING OF CONFORMAL POWER DELIVERY STRUCTURES

IN SITU INDUCTOR STRUCTURE IN BUILDUP POWER PLANES

CONFORMAL POWER DELIVERY STRUCTURES

CONFORMAL POWER DELIVERY STRUCTURES INCLUDING EMBEDDED PASSIVE DEVICES

Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures

CONFORMAL POWER DELIVERY STRUCTURES NEAR HIGH-SPEED SIGNAL TRACES

HEAT INSULATING INTERCONNECT FEATURES IN A COMPONENT OF A COMPOSITE IC DEVICE STRUCTURE

FEATURES FOR IMPROVING DIE SIZE AND ORIENTATION DIFFERENTIATION IN HYBRID BONDING SELF ASSEMBLY

UNIVERSAL HYBRID BONDING SURFACE LAYER USING AN ADAPTABLE INTERCONNECT LAYER FOR INTERFACE DISAGGREGATION

DEVICE, METHOD AND SYSTEM TO MITIGATE STRESS ON HYBRID BONDS IN A MULTI-TIER ARRANGEMENT OF CHIPLETS

THERMAL PERFORMANCE IN HYBRID BONDED 3D DIE STACKS

ACTIVE DEVICE LAYER AT INTERCONNECT INTERFACES