Los Gatos, California
United States
32
2026-01-22
The entities that hold a legal rights for patent applications filed by inventor Hoffmann Thomas:
Thomas Hoffmann from Los Gatos, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SEMICONDUCTOR LAYOUT IN FINFET TECHNOLOGIES
#2 | 2025-01-23Selectable Monolithic or External Scalable Die-to-Die Interconnection System Methodology
#3 | 2024-03-28Vertical Transistor Cell Structures Utilizing Topside and Backside Resources
#4 | 2024-03-28Vertical Transistors With Backside Power Delivery
#5 | 2024-02-08Selectable monolithic or external scalable die-to-die interconnection system methodology
#6 | 2023-12-21SEMICONDUCTOR LAYOUT IN FINFET TECHNOLOGIES
#7 | 2023-03-23Selectable monolithic or external scalable die-to-die interconnection system methodology
#8 | 2023-01-05Leakage current reduction in electrical isolation gate structures
#9 | 2020-12-24Semiconductor layout in FinFET technologies
#10 | 2020-10-15Leakage current reduction in electrical isolation gate structures
#11 | 2020-04-16Leakage current reduction in electrical isolation gate structures
#12 | 2019-03-07Semiconductor layout in FinFET technologies
#13 | 2018-09-13Semiconductor structure with multiple transistors having various threshold voltages
#14 | 2017-05-18Semiconductor structure with multiple transistors having various threshold voltages
#15 | 2017-01-26Method for fabricating a transistor device with a tuned dopant profile
#16 | 2016-10-20CMOS Structures and Processes Based on Selective Thinning
#17 | 2016-07-12CMOS structures and processes based on selective thinning
#18 | 2016-06-16Method for fabricating a transistor device with a tuned dopant profile
#19 | 2016-06-09Semiconductor structure with multiple transistors having various threshold voltages
#20 | 2016-05-19CMOS gate stack structures and processes
#21 | 2016-03-29Method for fabricating a transistor device with a tuned dopant profile
#22 | 2016-03-08CMOS gate stack structures and processes
#23 | 2015-11-19Method for fabricating a transistor with reduced junction leakage current
#24 | 2015-06-09Semiconductor devices having fin structures and fabrication methods thereof
#25 | 2015-03-05High uniformity screen and epitaxial layers for CMOS devices
#26 | 2014-12-23Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
#27 | 2014-11-11Transistor having reduced junction leakage and methods of forming thereof
#28 | 2014-05-27CMOS gate stack structures and processes
#29 | 2014-04-17Semiconductor structure with reduced junction leakage and method of fabrication thereof
#30 | 2014-03-27Deeply depleted MOS transistors having a screening layer and methods thereof
#31 | 2014-01-02Semiconductor structure with multiple transistors having various threshold voltages
#32 | 2013-12-24CMOS structures and processes based on selective thinning
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