Inventor profile of:

Aaron Yip

City:

Santa Clara, California

Country:

United States

Published Applications:

57

Last publication date:

2019-01-01

Top Assignees for applications by Aaron Yip

The entities that hold a legal rights for patent applications filed by inventor Yip Aaron:

Recent patent applications by Yip Aaron

Aaron Yip from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-01-01
US15693118
Physics

3D memory device including shared select gate connections between memory blocks

#2 | 2018-11-15
US20180331034A1
Electricity

Three dimensional storage cell array with highly dense and scalable word line design approach

#3 | 2017-10-05
US20170287833A1
Electricity

Three dimensional storage cell array with highly dense and scalable word line design approach

#4 | 2017-06-22
US20170178738A1
Physics

Reducing programming disturbance in memory devices

#5 | 2016-07-07
US20160196879A1
Physics

Three dimensional memory control circuitry

#6 | 2014-11-27
US20140351663A1
Physics

Single check memory devices and methods

#7 | 2014-05-29
US20140146612A1
Physics

Three dimensional memory control circuitry

#8 | 2014-04-10
US20140098606A1
Physics

Reducing programming disturbance in memory devices

#9 | 2014-01-02
US20140003151A1
Physics

Select gate programming in a memory device

#10 | 2012-12-20
US20120320685A1
Physics

Erase operation control sequencing apparatus, systems, and methods

#11 | 2012-08-30
US20120221779A1
Physics

Programming memory devices

#12 | 2012-06-28
US20120163076A1
Physics

Single check memory devices and methods

#13 | 2012-03-22
US20120069659A1
Physics

Memory with interleaved read and redundant columns

#14 | 2012-02-23
US20120044769A1
Physics

Multi-pass programming in a memory device

#15 | 2011-10-13
US20110249503A1
Physics

Select gate programming in a memory device

#16 | 2011-09-29
US20110235433A1
Physics

Verifying an erase threshold in a memory device

#17 | 2011-08-04
US20110188320A1
Physics

Memory devices and methods of their operation including selective compaction verify operations

#18 | 2011-06-30
US20110158003A1
Physics

Method of erasing memory cell

#19 | 2011-01-27
US20110019474A1
Physics

Flash memory device with redundant columns

#20 | 2011-01-13
US20110007562A1
Physics

Dynamic wordline start voltage for nand programming

#21 | 2010-12-02
US20100302844A1
Physics

Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling

#22 | 2010-11-25
US20100296348A1
Physics

Erase operation control sequencing apparatus, systems, and methods

#23 | 2010-08-12
US20100202214A1
Physics

Verifying an erase threshold in a memory device

#24 | 2010-06-10
US20100142280A1
Physics

Programming memory devices

#25 | 2010-05-27
US20100128523A1
Physics

Multi-pass programming in a memory device

#26 | 2010-03-11
US20100061155A1
Physics

Memory array segmentation and methods

#27 | 2010-01-28
US20100020609A1
Physics

Flash memory device with redundant columns

#28 | 2009-12-17
US20090310416A1
Physics

Selective threshold voltage verification and compaction

#29 | 2009-10-01
US20090244982A1
Physics

Memory block reallocation in a flash memory device

#30 | 2009-08-27
US20090216948A1
Physics

Method for substantially uninterrupted cache readout

#31 | 2009-06-18
US20090154247A1
Physics

Programming memory devices

#32 | 2009-06-04
US20090141559A1
Physics

Verifying an erase threshold in a memory device

#33 | 2009-02-12
US20090043975A1
Physics

Memory device trims

#34 | 2008-10-16
US20080253196A1
Physics

Method and apparatus for charging large capacitances

#35 | 2008-07-31
US20080181020A1
Physics

Erase operation control sequencing apparatus, systems, and methods

#36 | 2008-06-26
US20080151638A1
Physics

Selective threshold voltage verification and compaction

#37 | 2008-06-05
US20080130373A1
Physics

Programming memory devices

#38 | 2008-03-27
US20080074933A1
Physics

Random cache read

#39 | 2008-01-31
US20080025104A1
Physics

Method and apparatus for charging large capacitances

#40 | 2007-12-27
US20070300012A1
Physics

Method for substantially uninterrupted cache readout

#41 | 2007-12-13
US20070285988A1
Physics

Bitline exclusion in verification operation

#42 | 2007-11-22
US20070268732A1
Physics

Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling

#43 | 2007-08-09
US20070183202A1
Physics

Memory array segmentation and methods

#44 | 2007-04-12
US20070081411A1
Physics

Memory block reallocation in a flash memory device

#45 | 2007-03-01
US20070047326A1
Physics

Programming memory devices

#46 | 2007-03-01
US20070047311A1
Physics

Selective threshold voltage verification and compaction

#47 | 2007-02-08
US20070030739A1
Physics

Method of comparison between cache and data register for non-volatile memory

#48 | 2006-12-21
US20060285390A1
Physics

Bitline exclusion in verification operation

#49 | 2006-11-16
US20060256633A1
Physics

Handling defective memory blocks of NAND memory devices

#50 | 2006-11-16
US20060256620A1
Physics

Programming memory devices

#51 | 2006-11-02
US20060245290A1
Physics

Memory block reallocation in a flash memory device

#52 | 2006-11-02
US20060245272A1
Physics

Method of comparison between cache and data register for non-volatile memory

#53 | 2006-11-02
US20060245270A1
Physics

Random cache read

#54 | 2006-02-02
US20060023504A1
Physics

Non-volatile programmable fuse apparatus in a flash memory with pairs of supercells programmed in a complementary fashion

#55 | 2006-01-19
US20060015691A1
Physics

Memory device trims

#56 | 2005-12-29
US20050286337A1
Physics

Handling defective memory blocks of NAND memory devices

#57 | 2005-04-12
US10903395
-

Non-volatile programmable fuse apparatus in a memory device

InventorID:

594665 ⎘