Austin, Texas
United States
56
2016-12-08
The entities that hold a legal rights for patent applications filed by inventor Col Gerard M.:
Gerard M. Col from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
#2 | 2016-12-01Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
#3 | 2016-12-01Mechanism to preclude load replays dependent on page walks in an out-of-order processor
#4 | 2016-12-01Apparatus and method for programmable load replay preclusion
#5 | 2016-12-01Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor
#6 | 2016-12-01Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor
#7 | 2016-12-01Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor
#8 | 2016-12-01Load replay precluding mechanism
#9 | 2016-12-01Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
#10 | 2016-12-01Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor
#11 | 2016-11-24Mechanism to preclude shared RAM-dependent load replays in an out-of-order processor
#12 | 2016-11-24Mechanism to preclude I/O-dependent load replays in an out-of-order processor
#13 | 2016-07-21Power saving mechanism to reduce load replays in out-of-order processor
#14 | 2016-06-16Programmable load replay precluding mechanism
#15 | 2016-06-16Apparatus and method for programmable load replay preclusion
#16 | 2016-06-16Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor
#17 | 2016-06-16Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor
#18 | 2016-06-16Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
#19 | 2016-06-16Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor
#20 | 2016-06-16Mechanism to preclude shared ram-dependent load replays in an out-of-order processor
#21 | 2016-06-16Power saving mechanism to reduce load replays in out-of-order processor
#22 | 2016-06-16Programmable load replay precluding mechanism
#23 | 2016-06-16Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor
#24 | 2016-06-16Mechanism to preclude load replays dependent on page walks in an out-of-order processor
#25 | 2016-06-16Load replay precluding mechanism
#26 | 2016-06-16Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
#27 | 2016-06-16Mechanism to preclude I/O-dependent load replays in an out-of-order processor
#28 | 2016-06-16Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
#29 | 2015-12-03Processor that leapfrogs MOV instructions
#30 | 2014-05-01Microprocessor that translates conditional load/store instructions into variable number of microinstructions
#31 | 2014-05-01Conditional store instructions in an out-of-order execution microprocessor
#32 | 2014-01-09Conditional load instructions in an out-of-order execution microprocessor
#33 | 2012-10-11Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor
#34 | 2012-10-11Efficient conditional ALU instruction in read-port limited register file microprocessor
#35 | 2012-10-11Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
#36 | 2011-03-10Apparatus and method for detection and correction of denormal speculative floating point operand
#37 | 2011-02-10Out-of-order X86 microprocessor with fast shift-by-zero handling
#38 | 2011-02-10Microprocessor with ALU integrated into store unit
#39 | 2011-02-10Microprocessor with ALU integrated into load unit
#40 | 2010-12-02Microprocessor that refrains from executing a mispredicted branch in the presence of an older unretired cache-missing load instruction
#41 | 2010-11-25Microprocessor with microinstruction-specifiable non-architectural condition code flag register
#42 | 2010-08-12Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register
#43 | 2010-05-27Out-of-order execution microprocessor that selectively initiates instruction retirement early
#44 | 2010-03-18Microprocessor with fused store address/store data microinstruction
#45 | 2009-10-08Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture
#46 | 2009-08-13Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions
#47 | 2006-09-12Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions
#48 | 2006-08-29Pipelined microprocessor, apparatus, and method for generating early status flags
#49 | 2006-05-30Paired load-branch operation for indirect near jumps
#50 | 2005-11-24Apparatus and method for masked move to and from flags register in a processor
#51 | 2005-10-13Apparatus and method for masked move to and from flags register in a processor
#52 | 2005-09-22Processor including fallback branch prediction mechanism for far jump and far call instructions
#53 | 2005-08-18Pipelined microprocessor, apparatus, and method for generating early instruction results
#54 | 2005-08-11Pop-compare micro instruction for repeat string operations
#55 | 2005-06-30Processor including branch prediction mechanism for far jump and far call instructions
#56 | 2005-06-30Microprocessor apparatus and method for accelerating execution of repeat string instructions
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