Noida
India
27
2025-02-06
The entities that hold a legal rights for patent applications filed by inventor KUMAR Anand:
Anand KUMAR from Noida, IN has applied for patents for these inventions. The list has both pending applications and granted patents:
MULTIPLEXER WITH HIGHLY LINEAR ANALOG SWITCH
#2 | 2024-10-31METHODS, SYSTEMS, AND APPARATUSES FOR CALIBRATING RESISTOR-CAPACITOR (RC) CIRCUITS
#3 | 2023-12-28Low power crystal oscillator
#4 | 2023-12-21Low power crystal oscillator with automatic amplitude control
#5 | 2023-10-12Multiplexer with highly linear analog switch
#6 | 2023-05-25Low noise phase lock loop (PLL) circuit
#7 | 2023-03-23Low power crystal oscillator
#8 | 2022-11-03High performance phase locked loop for millimeter wave applications
#9 | 2022-09-29MULTIPLEXER CIRCUIT USING A TRANSMISSION GATE CIRCUIT WITH A SELECTIVELY BOOSTED SWITCH CONTROL SIGNAL
#10 | 2022-06-30High performance phase locked loop for millimeter wave applications
#11 | 2022-06-02Multiplexer with highly linear analog switch
#12 | 2021-09-09Programmable-on-the-fly fractional divider in accordance with this disclosure
#13 | 2021-08-12Adaptive low power common mode buffer
#14 | 2020-12-17Adaptive low power common mode buffer
#15 | 2020-07-23Low power crystal oscillator
#16 | 2020-03-05Locked loop circuit with reference signal provided by un-trimmed oscillator
#17 | 2019-03-28Calibration of a voltage controlled oscillator to trim the gain thereof, using a phase locked loop and a frequency locked loop
#18 | 2018-10-04Locked loop circuit with reference signal provided by un-trimmed oscillator
#19 | 2018-06-07Spread spectrum clock generator
#20 | 2018-03-01Spread spectrum clock generator
#21 | 2016-04-26Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature
#22 | 2016-04-21Dual gate FD-SOI transistor
#23 | 2015-09-24Clock glitch and loss detection circuit
#24 | 2015-05-14DUAL GATE FD-SOI TRANSISTOR
#25 | 2014-01-16Phase locked loop circuit with reduced jitter
#26 | 2011-06-16On-the-fly frequency switching while maintaining phase and frequency lock
#27 | 2007-08-30System and method for multiple-phase clock generation
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