Andy Wei

Siloxane and organic-based MOL contact patterning

Metal gate for robust ESD protection

FORMING SOURCE/DRAIN REGIONS WITH SINGLE RETICLE AND RESULTING DEVICE

Semiconductor device having a high-K gate dielectric above an STI region

Methods for fabricating integrated circuits

Method of forming self-aligned contacts for a semiconductor device

Methods for fabricating integrated circuits having gate to active and gate to gate interconnects

Threshold voltage adjustment in a Fin transistor by corner implantation

High-K metal gate electrode structures formed by early cap layer adaptation

Semiconductor device comprising metal gates and a silicon containing resistor formed on an isolation structure

High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology

Metal gate stack formation for replacement gate technology

SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Semiconductor device comprising self-aligned contact elements

Transistor with embedded Si/Ge material having enhanced across-substrate uniformity

Fin-transistor formed on a patterned STI region by late fin etch

High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials

Self-aligned fin transistor formed on a bulk substrate by late fin etch

Encapsulation of closely spaced gate electrode structures

Shallow pn junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process

Transistor with embedded strain-inducing material formed in diamond-shaped cavities based on a pre-amorphization

Self-aligned multiple gate transistor formed on a bulk substrate

Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach

Replacement gate approach for high-k metal gate stacks by avoiding a polishing process for exposing the placeholder material

Methods of forming efuse devices

Semiconductor device comprising metal gate structures formed by a replacement gate approach and efuses including a silicide

Contact bars with reduced fringing capacitance in a semiconductor device

Method for forming a transistor with recessed drain and source areas and non-conformal metal silicide regions

ADJUSTMENT OF TRANSISTOR CHARACTERISTICS BASED ON A LATE WELL IMPLANTATION

SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device

Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal

Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy

Semiconductor resistors formed at a lower height level in a semiconductor device comprising metal gates

Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement

TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SUPERIOR IMPLANTATION MASKING EFFECT

Forming semiconductor resistors in a semiconductor device comprising metal gates by increasing etch resistivity of the resistors

Work function adjustment in high-k gate stacks including gate dielectrics of different thickness

Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors

Semiconductor device comprising metal gates and a silicon containing resistor formed on an isolation structure

Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility

Graded well implantation for asymmetric transistors having reduced gate electrode pitches

Short channel transistor with reduced length variation by using amorphous electrode material during implantation

Tensile strain source using silicon/germanium in globally strained silicon

Method of forming a field effect transistor

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Multiple gate transistor having fins with a length defined by the gate electrode

Recessed drain and source areas in combination with advanced silicide formation in transistors

HIGH-K ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL DURING FABRICATION OF TRANSISTORS

Transistor with embedded SI/GE material having enhanced across-substrate uniformity

Transistor with embedded Si/Ge material having reduced offset to the channel region

Semiconductor device comprising a buried poly resistor

Structured strained substrate for forming strained transistors with reduced thickness of active layer

Shallow PN junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process

CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistor

CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND NON-CONFORMAL METAL SILICIDE REGIONS

Contact trenches for enhancing stress transfer in closely spaced transistors

Method for forming double gate and tri-gate transistors on a bulk substrate

In situ formed drain and source regions in a silicon/germanium containing transistor device

Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode

CMOS DEVICE COMPRISING AN NMOS TRANSISTOR WITH RECESSED DRAIN AND SOURCE AREAS AND A PMOS TRANSISTOR HAVING A SILICON/GERMANIUM MATERIAL IN THE DRAIN AND SOURCE AREAS

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors

Tensile strain source using silicon/germanium in globally strained silicon

METHOD OF FORMING HIGH-K GATE ELECTRODE STRUCTURES AFTER TRANSISTOR FABRICATION

Method for self-aligned removal of a high-K gate dielectric above an STI region

Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device

Method of forming CMOS device having gate insulation layers of different type and thickness

Blocking pre-amorphization of a gate electrode of a transistor

Enhanced transistor performance of N-channel transistors by using an additional layer above a dual stress liner in a semiconductor device

TECHNIQUE FOR ENHANCING DOPANT ACTIVATION BY USING MULTIPLE SEQUENTIAL ADVANCED LASER/FLASH ANNEAL PROCESSES

SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device

Method for creating tensile strain by repeatedly applied stress memorization techniques

SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto

Method for differential spacer removal by wet chemical etch process and device with differential spacer structure

Semiconductor device having a strained semiconductor alloy concentration profile

Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss

Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate

Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region

Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same

Formation of transistor having a strained channel region including a performance enhancing material composition utilizing a mask pattern

METHOD OF REDUCING A ROUGHNESS OF A SEMICONDUCTOR SURFACE

Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same

Method of forming a field effect transistor

SOI transistor having a reduced body potential and a method of forming the same

SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same

Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility

Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

Technique for providing stress sources in MOS transistors in close proximity to a channel region

Technique for forming a strained transistor by a late amorphization and disposable spacers

Transistor device having an increased threshold stability without drive current degradation

TECHNIQUE FOR REDUCING CRYSTAL DEFECTS IN STRAINED TRANSISTORS BY TILTED PREAMORPHIZATION

Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors

Technique for providing multiple stress sources in NMOS and PMOS transistors

Embedded strain layer in thin SOI transistors and a method of forming the same

Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors

Technique for forming a contact insulation layer with enhanced stress transfer efficiency

Gate structure and a transistor having asymmetric spacer elements and methods of forming the same