Inventor profile of:

HeeJo Chi

City:

Daejeon-si

Country:

South Korea

Published Applications:

11

Last publication date:

2013-01-31

Top Assignees for applications by HeeJo Chi

The entities that hold a legal rights for patent applications filed by inventor Chi HeeJo:

Recent patent applications by Chi HeeJo

HeeJo Chi from Daejeon-si, KR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-01-31
US20130026654A1
Electricity

Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die

#2 | 2012-02-16
US20120038034A1
Electricity

Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die

#3 | 2011-12-08
US20110298105A1
Electricity

Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure

#4 | 2010-11-04
US20100276792A1
Electricity

Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure

#5 | 2010-10-14
US20100258928A1
Electricity

Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof

#6 | 2010-09-30
US20100244222A1
Electricity

Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof

#7 | 2010-09-23
US20100237500A1
Electricity

Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site

#8 | 2010-09-23
US20100237483A1
Electricity

Integrated circuit packaging system with an interposer and method of manufacture thereof

#9 | 2010-09-23
US20100237481A1
Electricity

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF

#10 | 2010-09-09
US20100224975A1
Electricity

Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof

#11 | 2008-12-25
US20080315406A1
Electricity

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE

InventorID:

61422 ⎘