STATS CHIPPAC, LTD.

Semiconductor device and method of forming substrate including embedded component with symmetrical structure

Semiconductor device and method of forming a package in-fan out package

Double-sided semiconductor package and dual-mold method of making same

Semiconductor device and method of forming PoP semiconductor device with RDL over top package

Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package

Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package

Integrated circuit packaging system with insulated trace and method of manufacture thereof

Semiconductor device and method of forming WLCSP with semiconductor die embedded within interconnect structure

Semiconductor device and method of forming MEMS package

Semiconductor device and method of forming shielding layer over integrated passive device using conductive channels

Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die

Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form

Integrated circuit packaging system with interposer structure and method of manufacture thereof

Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield

Integrated circuit packaging system with package stacking

Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLB-MLP)

Integrated circuit packaging system with pre-molded leadframe and method of manufacture thereof

Semiconductor device and method of fabricating 3D package with short cycle time and high yield

Semiconductor device and method of fabricating 3D package with short cycle time and high yield

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region

Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die

Integrated circuit packaging system with coreless substrate and method of manufacture thereof

Integrated circuit packaging system with electrical interface and method of manufacture thereof

Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof

Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Integrated circuit through-substrate via system with a buffer layer and method of manufacture thereof

Semiconductor device and method of forming double-sided fan-out wafer level package

Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric characteristics

Method of manufacture of support system with fine pitch

Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits

Semiconductor device and method of forming adhesive layer over insulating layer for bonding carrier to mixed surfaces of semiconductor die and encapsulant

Integrated circuit packaging system with pattern-through-mold and method of manufacture thereof

Integrated circuit packaging system with under bump metallization and method of manufacture thereof

Integrated circuit packaging system with leadframe and method of manufacture thereof

Methods of mitigating defects for semiconductor packages

Integrated circuit packaging system with trace protection layer and method of manufacture thereof

Integrated circuit system with debonding adhesive and method of manufacture thereof

Semiconductor device and method of forming bump-on-lead interconnection

Integrated circuit packaging system with coreless substrate and method of manufacture thereof

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring

Integrated circuit packaging system with fiber-less substrate and method of manufacture thereof

Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package

Integrated circuit packaging system with plated leads and method of manufacture thereof

Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure

Semiconductor device and method of forming microelectromechanical systems (MEMS) package

Integrated circuit packaging system with void prevention mechanism and method of manufacture thereof

Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers

Leadframe system with warp control mechanism and method of manufacture thereof

Integrated circuit packaging system with package underfill and method of manufacture thereof

Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)

Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation

Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die

Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief

Integrated circuit packaging system with routable traces and method of manufacture thereof

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Method of manufacture of integrated circuit packaging system with plasma processing

Integrated circuit packaging system with posts and method of manufacture thereof

Integrated circuit system with debonding adhesive and method of manufacture thereof

Dual-sided film-assist molding process

Semiconductor device and method of forming build-up interconnect structures over a temporary substrate

Semiconductor device and method of forming stress relief layer between die and interconnect structure

Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package

Semiconductor device and method of wafer thinning involving edge trimming and CMP

Semiconductor device and method of making embedded wafer level chip scale packages

Semiconductor device and method of reducing warpage using a silicon to encapsulant ratio

Integrated circuit packaging system with embedded component and method of manufacture thereof

Integrated circuit packaging system with underfill and method of manufacture thereof

Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package

Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die

Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP

Semiconductor device and method of forming wire bondable fan-out EWLB package

Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

Semiconductor device and method of forming a shielding layer between stacked semiconductor die

Semiconductor device and method of forming conductive layer over substrate with vents to channel bump material and reduce interconnect voids

Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration

Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer

Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP

Semiconductor device and method of controlling warpage in reconstituted wafer

Semiconductor device and method of forming dual fan-out semiconductor package

Integrated circuit packaging system with heat spreader and method of manufacture thereof

Integrated circuit packaging system with side solderable leads and method of manufacture thereof

Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer

Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation

Semiconductor device and method of forming pad layout for flipchip semiconductor die

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

Methods of forming solder balls in semiconductor packages

Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure

Semiconductor device and method of forming through mold hole with alignment and dimension control

Semiconductor device and method of forming thermal lid for balancing warpage and thermal management

Integrated circuit packaging system with trenched leadframe and method of manufacture thereof

Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation