Fishkill, New York
United States
36
2014-02-06
The entities that hold a legal rights for patent applications filed by inventor Pal Rohit:
Rohit Pal from Fishkill, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Reconfigurable microactuator and method of configuring same
#2 | 2012-08-02Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization
#3 | 2012-05-24Method of manufacturing a transistor device having asymmetric embedded strain elements
#4 | 2012-05-17Gate etch optimization through silicon dopant profile change
#5 | 2012-05-10Fabrication of semiconductors with high-K/metal gate electrodes
#6 | 2011-08-25METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH REDUCED GATE HEIGHT, AND RELATED FABRICATION METHODS
#7 | 2011-07-14Transistor device having asymmetric embedded strain elements and related manufacturing method
#8 | 2011-05-26Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
#9 | 2011-04-28Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
#10 | 2011-04-14Methods for protecting film layers while removing hardmasks during fabrication of semiconductor devices
#11 | 2011-03-17Fabrication of semiconductors with high-K/metal gate electrodes
#12 | 2010-11-25Gate etch optimization through silicon dopant profile change
#13 | 2010-11-18Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization
#14 | 2010-09-30Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
#15 | 2010-08-19Methods for fabricating MOS devices having highly stressed channels
#16 | 2010-08-19Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same
#17 | 2010-05-06Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
#18 | 2010-04-22Stress enhanced transistor
#19 | 2010-04-15Semiconductor devices having faceted silicide contacts, and related fabrication methods
#20 | 2010-04-01Methods for fabricating MOS devices having highly stressed channels
#21 | 2010-03-11SEMICONDUCTOR TRANSISTOR DEVICE WITH IMPROVED ISOLATION ARRANGEMENT, AND RELATED FABRICATION METHODS
#22 | 2010-03-04Reconfigurable microactuator and method of configuring same
#23 | 2010-03-02Methods for fabricating MOS devices having epitaxially grown stress-inducing source and drain regions
#24 | 2010-01-21METAL OXIDE SEMICONDUCTOR DEVICES HAVING IMPLANTED CARBON DIFFUSION RETARDATION LAYERS AND METHODS FOR FABRICATING THE SAME
#25 | 2010-01-21Transistor device having asymmetric embedded strain elements and related manufacturing method
#26 | 2009-11-12Method of forming stepped recesses for embedded strain elements in a semiconductor device
#27 | 2009-11-12Method of controlling embedded material/gate proximity
#28 | 2009-10-15Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods
#29 | 2009-09-10METHOD AND APPARATUS FOR CONTROLLING STRESSED LAYER GATE PROXIMITY
#30 | 2009-07-09METHODS FOR FABRICATING SEMICONDUCTOR DEVICES USING THERMAL GRADIENT-INDUCING FILMS
#31 | 2009-07-02Methods for calibrating a process for growing an epitaxial silicon film and methods for growing an epitaxial silicon film
#32 | 2008-10-09METHOD AND APPARATUS FOR DETERMINING CHARACTERISTICS OF A STRESSED MATERIAL USING SCATTEROMETRY
#33 | 2008-10-02METHOD FOR PRESERVING PROCESSING HISTORY ON A WAFER
#34 | 2008-09-11STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION
#35 | 2008-06-19Stress enhanced transistor and methods for its fabrication
#36 | 2008-05-22Stress enhanced MOS transistor and methods for its fabrication
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