San Jose, California
United States
113
2025-11-13
The entities that hold a legal rights for patent applications filed by inventor Kumar Naveen:
Naveen Kumar from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
PROFILE-GUIDED QUANTIZATION OF NEURAL NETWORKS
#2 | 2024-08-22DATA STORAGE DEVICE
#3 | 2024-03-21Bit flipping decoder using channel information
#4 | 2024-03-14Iteration dependent bitwise bit flipping decoder
#5 | 2024-02-22DEVICE PLACEMENT OPTIMIZATION WITH REINFORCEMENT LEARNING
#6 | 2023-07-20Data storage device
#7 | 2023-04-13Mitigating edge layer effect in partially written blocks
#8 | 2023-02-28Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells
#9 | 2022-11-17Adaptive read disturb algorithm for NAND storage accounting for layer-based effect
#10 | 2022-04-28Synchronous hardware event collection
#11 | 2021-10-21Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells
#12 | 2021-08-12Distributed hardware tracing
#13 | 2020-11-26Data storage device
#14 | 2020-11-26Data storage device
#15 | 2020-10-08Soft chip-kill recovery for multiple wordlines failure
#16 | 2020-09-03Device placement optimization with reinforcement learning
#17 | 2020-07-02Soft chipkill recovery for bitline failures
#18 | 2020-06-11Memory system and method for read operation based on grouping of word lines
#19 | 2020-03-19Memory system to process multiple word line failures with limited storage and method of operating such memory system
#20 | 2020-02-27Distributed hardware tracing
#21 | 2020-02-06Dynamic neighbor and bitline assisted correction for NAND flash storage
#22 | 2020-01-16Synchronous hardware event collection
#23 | 2019-12-19Memory system with adaptive read-threshold scheme and method of operating such memory system
#24 | 2019-12-12Data storage device
#25 | 2019-12-12Decoder for memory system and method thereof
#26 | 2019-11-07Memory system with hybrid iterative decoding capability and method of operating such memory system
#27 | 2019-11-07Memory system with deep learning based interference correction capability and method of operating such memory system
#28 | 2019-11-07Encoder and decoder for memory system and method thereof
#29 | 2019-11-07Neighbor assisted correction error recovery for memory system and method thereof
#30 | 2019-10-31Distributed hardware tracing
#31 | 2019-10-03Dynamic interleaver change for bit line failures in NAND flash storage
#32 | 2019-10-03Memory system and method for bad block management
#33 | 2019-10-03Device placement optimization with reinforcement learning
#34 | 2019-09-19Memory system with hybrid decoding scheme and method of operating such memory system
#35 | 2019-09-19Memory system with adaptive threshold decoding and method of operating such memory system
#36 | 2019-09-19Encoding method and system for memory device including QLC cells
#37 | 2019-09-19Memory system with hybrid decoding scheme with information exchange and method of operating such memory system
#38 | 2019-09-19LDPC decoding device, memory system including the same and method thereof
#39 | 2019-08-15Memory system with adaptive information propagation and method of operating such memory
#40 | 2019-07-11Encoding method and system for memory device including QLC cells
#41 | 2019-07-11Memory system with super chip-kill recovery and method of operating such memory system
#42 | 2019-07-11Retention aware block mapping in flash-based solid state drives
#43 | 2019-05-23Methods and memory systems for address mapping
#44 | 2019-05-23Garbage collection methods and memory systems for hybrid address mapping
#45 | 2019-05-23Soft chip-kill recovery for multiple wordlines failure
#46 | 2019-05-23Soft chip-kill recovery using concatenated codes
#47 | 2019-05-23Memory system with soft-read suspend scheme and method of operating such memory system
#48 | 2019-03-28Min-sum decoding for LDPC codes
#49 | 2019-03-28Memory system with on-the-fly error detection and termination and operating method thereof
#50 | 2019-03-28Memory system with decoders and method of operating such memory system and decoders
#51 | 2019-03-28Memory system decoding design and operating method thereof
#52 | 2019-03-28Method to select flash memory blocks for refresh after read operations
#53 | 2019-02-28Memory system with LDPC decoder and method of operating such memory system and LDPC decoder
#54 | 2019-02-28Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes
#55 | 2019-02-28Read disturb detection and recovery with adaptive thresholding for 3-D NAND storage
#56 | 2019-02-28Memory system with adaptive read-threshold scheme and method of operating such memory system
#57 | 2019-01-24Low-complexity LDPC encoder
#58 | 2018-12-25Memory system having feature boosting and operating method thereof
#59 | 2018-11-29Early termination of low-density parity-check (LDPC) decoding
#60 | 2018-11-29Generalized low-density parity-check (GLDPC) code with variable length constituents
#61 | 2018-11-29Deep learning for low-density parity-check (LDPC) decoding
#62 | 2018-10-18Symbol-based coding for NAND flash devices
#63 | 2018-10-04Synchronous hardware event collection
#64 | 2018-10-04Distributed hardware tracing
#65 | 2018-09-20State-based decoding of product codes
#66 | 2018-05-24Data mapping scheme for generalized product codes
#67 | 2018-05-10Bit-flipping LDPC decoding algorithm with hard channel information
#68 | 2018-05-10Performing Local Power Gating In A Processor
#69 | 2018-05-10Performing local power gating in a processor
#70 | 2018-04-26Memory system with LDPC decoder and operating method thereof
#71 | 2018-02-15Page health prediction using product codes decoder in NAND flash storage
#72 | 2018-02-15Low latency soft decoder architecture for generalized product codes
#73 | 2018-02-15Redundant bytes utilization in error correction code
#74 | 2018-01-23Distributed hardware tracing
#75 | 2017-12-28Data dependency mitigation in parallel decoders for flash storage
#76 | 2017-12-28Performing Local Power Gating In A Processor
#77 | 2017-11-16System and method for parallel decoding of codewords sharing common data
#78 | 2017-10-12Optimization of low density parity-check code encoder based on a search for an independent set of nodes
#79 | 2017-09-28Soft decoder for generalized product codes
#80 | 2017-09-28Performance optimization in soft decoding of error correcting codes
#81 | 2017-09-28Hybrid soft decoding algorithm for multiple-dimension TPC codes
#82 | 2017-09-28Soft decoder parameter optimization for product codes
#83 | 2017-09-28Techniques for low-latency chase decoding of turbo product codes with soft information
#84 | 2017-09-14Code reconstruction scheme for multiple code rate TPC decoder
#85 | 2017-08-24Instruction and logic for a binary translation mechanism for control-flow security
#86 | 2017-08-03Data dependency mitigation in decoder architecture for generalized product codes for flash storage
#87 | 2017-07-06Techniques for miscorrection detection for constituent codewords in product codes
#88 | 2017-06-22Techniques for low complexity soft decoder for turbo product codes
#89 | 2017-06-01Techniques for low complexity turbo product code decoding
#90 | 2017-02-14Decoding of turbo product codes using miscorrection detection
#91 | 2017-01-31Stopping rules for turbo product codes
#92 | 2016-12-08One-shot decoder for two-error-correcting BCH codes
#93 | 2016-11-24Performance optimization in soft decoding for turbo product codes
#94 | 2016-11-24Generalized product codes for flash storage
#95 | 2016-11-17Miscorrection avoidance for turbo product codes
#96 | 2016-08-25Scheme to avoid miscorrection for turbo product codes
#97 | 2016-08-18Instruction and logic for a binary translation mechanism for control-flow security
#98 | 2016-06-09Turbo product codes for NAND flash
#99 | 2016-05-26Apparatus and method for turbo product codes
#100 | 2016-05-12Optimal read threshold estimation
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