Nitin CHAWLA

SHARED ROUTING AND SENSING IN A MULTI-TILE DIGITAL IN-MEMORY COMPUTATION (DIMC) NEURAL PROCESSING UNIT (NPU)

RANDOM ANALOG-TO-DIGITAL CONVERTER COMPUTE CYCLE MANAGEMENT FOR AN ANALOG IN-MEMORY COMPUTATION PROCESSING SYSTEM

SELF-CLOCKING IN A MULTI-TILE IN-MEMORY COMPUTATION (IMC) NEURAL PROCESSING UNIT (NPU)

ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPERATION BY ACCOUNTING FOR VARIATION IN READ CURRENT

BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

DYNAMIC BIT PRECISION CONTROL FOR AN IN-MEMORY COMPUTATION PROCESSING SYSTEM

RANDOMIZED SEQUENCE FOR ROW AND/OR COLUMN ADDRESSING IN A DIGITAL IN-MEMORY COMPUTATION PROCESSING SYSTEM

MEMORY ARCHITECTURE WITH A DIGITAL IN-MEMORY COMPUTATION PROCESSING MODE AND A COLUMN MULTIPLEXING MEMORY ACCESS MODE

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK MEMORY

SCRAMBLED DUMMY COLUMN MEMORY ARCHITECTURE FOR AN IN-MEMORY COMPUTATION PROCESSING SYSTEM

RANDOMIZED DATA POLARITY INVERSION OF COMPUTATIONAL WEIGHT DATA IN A DIGITAL IN-MEMORY COMPUTATION PROCESSING SYSTEM

TILED IN-MEMORY COMPUTATION PROCESSING SYSTEM WITH RANDOMIZED CLOCK STAGGERING AND OUTPUT BINDING

ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY INPUT/OUTPUT

SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULATION FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT

TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDENT ON OPERATIONAL MODE SELECTION

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK MEMORY

ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEMORY ARCHITECTURE

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE AND DIGITAL IN-MEMORY COMPUTATION PROCESSING MODE

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE AND DIGITAL IN-MEMORY COMPUTATION PROCESSING MODE

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY INPUT/OUTPUT

TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM

BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY SEGMENTATION

BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY SEGMENTATION AND LOCAL COMPUTE TILE READ BASED ON WEIGHTED CURRENT

ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPERATION BY ACCOUNTING FOR VARIATION IN READ CURRENT

Computing system power management device, system and method

In-memory compute array with integrated bias elements

Bit-cell architecture based in-memory compute

Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

Elements for in-memory compute

Tagged memory operated at lower vmin in error tolerant system

Memory management device, system and method

Streaming access memory device, system and method

Computing system power management device, system and method

Variable clock adaptation in neural network processors

Tagged memory operated at lower vmin in error tolerant system

Memory management device, system and method

In-memory compute array with integrated bias elements

Elements for in-memory compute

Deep convolutional network heterogeneous architecture

Adaptive multi-stage slack borrowing for high performance error resilient computing

Adaptive multi-stage slack borrowing for high performance error resilient computing

Calibration arrangement

Fail safe adaptive voltage/frequency system

Fail safe adaptive voltage/frequency system

Spread spectrum clock generation

Device for implementing a sum of products expression